FPGA/verilog-pcie
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Only store on valid transfer in

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Alex Forencich 2018-11-26 13:18:38 -08:00
parent 1dcc091201
commit 24f709573c
1 changed files with 1 additions and 1 deletions
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rtl/pcie_us_axi_master_rd.v
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@ -662,7 +662,7 @@ always @* begin
m_axi_rready_next = m_axis_cc_tready_int_early && input_active_reg;
if (m_axis_cc_tready_int_reg && ((m_axi_rready && m_axi_rvalid) || !input_active_reg)) begin
transfer_in_save = 1'b1;
transfer_in_save = m_axi_rready && m_axi_rvalid;
if (AXIS_PCIE_DATA_WIDTH == 256 && bubble_cycle_reg) begin
// bubble cycle; store input data and update input cycle count