From 24f709573c4027785fa5035b10e137d457fd0e8b Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Mon, 26 Nov 2018 13:18:38 -0800 Subject: [PATCH] Only store on valid transfer in --- rtl/pcie_us_axi_master_rd.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rtl/pcie_us_axi_master_rd.v b/rtl/pcie_us_axi_master_rd.v index ed5e9f5..406872d 100644 --- a/rtl/pcie_us_axi_master_rd.v +++ b/rtl/pcie_us_axi_master_rd.v @@ -662,7 +662,7 @@ always @* begin m_axi_rready_next = m_axis_cc_tready_int_early && input_active_reg; if (m_axis_cc_tready_int_reg && ((m_axi_rready && m_axi_rvalid) || !input_active_reg)) begin - transfer_in_save = 1'b1; + transfer_in_save = m_axi_rready && m_axi_rvalid; if (AXIS_PCIE_DATA_WIDTH == 256 && bubble_cycle_reg) begin // bubble cycle; store input data and update input cycle count