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Fix bug in DMA client source when AXI stream width matches RAM interface width

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This commit is contained in:
Alex Forencich 2021-02-16 01:25:07 -08:00
parent 20b2414d7a
commit 33bc8c21ae
1 changed files with 5 additions and 1 deletions
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6
rtl/dma_client_axis_source.v
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@ -406,7 +406,11 @@ always @* begin
ram_mask_next = {SEG_COUNT{1'b1}};
end
m_axis_read_data_tdata_int = ram_rd_resp_data >> (((addr_reg >> PART_OFFSET_WIDTH) & {PART_COUNT_WIDTH{1'b1}}) * AXIS_DATA_WIDTH);
if (PART_COUNT > 1) begin
m_axis_read_data_tdata_int = ram_rd_resp_data >> (((addr_reg >> PART_OFFSET_WIDTH) & {PART_COUNT_WIDTH{1'b1}}) * AXIS_DATA_WIDTH);
end else begin
m_axis_read_data_tdata_int = ram_rd_resp_data;
end
m_axis_read_data_tkeep_int = {AXIS_KEEP_WIDTH_INT{1'b1}};
m_axis_read_data_tvalid_int = 1'b1;