FPGA/verilog-pcie
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Mask out old field value

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This commit is contained in:
Alex Forencich 2018-10-15 13:52:05 -07:00
parent 22850707a6
commit 4adaa480ca
1 changed files with 1 additions and 1 deletions
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tb/pcie.py
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@ -3637,7 +3637,7 @@ class RootComplex(Switch):
yield self.capability_write(dev, MSI_CAP_ID, 8, struct.pack('<L', self.msi_msg_limit))
# enable and set enabled messages
yield self.capability_write(dev, MSI_CAP_ID, 0, struct.pack('<L', msg_ctrl | 1 << 16 | msi_mmcap << 20))
yield self.capability_write(dev, MSI_CAP_ID, 0, struct.pack('<L', (msg_ctrl & ~(7 << 20)) | 1 << 16 | msi_mmcap << 20))
ti.msi_addr = self.msi_addr
ti.msi_data = self.msi_msg_limit