FPGA/verilog-pcie
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Add timing constraints for LED driver

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This commit is contained in:
Alex Forencich 2020-09-22 22:13:54 -07:00
parent c7594c77ab
commit 4ae9ec818c
2 changed files with 13 additions and 0 deletions
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1
example/fb2CG/fpga_axi/fpga/Makefile
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@ -30,6 +30,7 @@ SYN_FILES += lib/pcie/rtl/pulse_merge.v
# XDC files
XDC_FILES = fpga.xdc
XDC_FILES += led.tcl
# IP
IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl

12
example/fb2CG/fpga_axi/led.tcl Normal file
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@ -0,0 +1,12 @@
# Timing constraints for led_sreg_driver
foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == led_sreg_driver || REF_NAME == led_sreg_driver)}] {
puts "Inserting timing constraints for led_sreg_driver instance $inst"
set select_ffs [get_cells "$inst/led_sync_reg_1_reg[*] $inst/led_sync_reg_2_reg[*]"]
if {[llength $select_ffs]} {
set_property ASYNC_REG TRUE $select_ffs
set_false_path -from [all_registers] -to [get_cells "$inst/led_sync_reg_1_reg[*]"]
}
}