FPGA/verilog-pcie
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Fix completion handling in function

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This commit is contained in:
Alex Forencich 2019-07-15 20:25:23 -07:00
parent a0bd74a198
commit 4bf1205514
1 changed files with 3 additions and 2 deletions
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5
tb/pcie.py
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@ -1540,8 +1540,9 @@ class Function(PMCapability, PCIECapability):
self.current_tag = 0
self.rx_cpl_queues = [[]]*256
self.rx_cpl_sync = [Signal(False)]*256
self.rx_cpl_queues = [[] for k in range(256)]
self.rx_cpl_sync = [Signal(False) for k in range(256)]
self.rx_tlp_handler = {}
self.capabilities = PcieCapList()