FPGA/verilog-pcie
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Fix RC channel sideband byte enables

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This commit is contained in:
Alex Forencich 2019-10-11 14:16:44 -07:00
parent b7a505acfd
commit 603a6e18e2
1 changed files with 24 additions and 4 deletions
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28
tb/pcie_us.py
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@ -530,12 +530,22 @@ class TLP_us(TLP):
# compute byte enables
byte_en = [0]*3
first_be = (0xf << (self.lower_address&3)) & 0xf
if self.byte_count+(self.lower_address&3) > self.length*4:
last_be = 0xf
else:
last_be = 0xf >> ((self.byte_count+self.lower_address)&3)
if len(self.data) == 1:
first_be = first_be & last_be
last_be = 0
if len(self.data) >= 1:
byte_en += [self.first_be]
byte_en += [first_be]
if len(self.data) > 2:
byte_en += [0xf] * (len(self.data)-2)
if len(self.data) > 1:
byte_en += [self.last_be]
byte_en += [last_be]
# compute parity
parity = [dword_parity(d) ^ 0xf for d in pkt.data]
@ -596,12 +606,22 @@ class TLP_us(TLP):
# compute byte enables
byte_en = [0]*3
first_be = (0xf << (self.lower_address&3)) & 0xf
if self.byte_count+(self.lower_address&3) > self.length*4:
last_be = 0xf
else:
last_be = 0xf >> ((self.byte_count+self.lower_address)&3)
if len(self.data) == 1:
first_be = first_be & last_be
last_be = 0
if len(self.data) >= 1:
byte_en += [self.first_be]
byte_en += [first_be]
if len(self.data) > 2:
byte_en += [0xf] * (len(self.data)-2)
if len(self.data) > 1:
byte_en += [self.last_be]
byte_en += [last_be]
# compute parity
parity = [dword_parity(d) ^ 0xf for d in pkt.data]