From 6d98a7c0e680c75035e6cade97a75a600fa46bee Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Thu, 11 Feb 2021 00:14:36 -0800 Subject: [PATCH] Ensure output FIFOs use distributed RAM --- rtl/dma_client_axis_source.v | 6 ++++++ rtl/dma_if_pcie_us_wr.v | 4 ++++ 2 files changed, 10 insertions(+) diff --git a/rtl/dma_client_axis_source.v b/rtl/dma_client_axis_source.v index add750a..93477a3 100644 --- a/rtl/dma_client_axis_source.v +++ b/rtl/dma_client_axis_source.v @@ -495,11 +495,17 @@ reg out_fifo_half_full_reg = 1'b0; wire out_fifo_full = out_fifo_wr_ptr_reg == (out_fifo_rd_ptr_reg ^ {1'b1, {OUTPUT_FIFO_ADDR_WIDTH{1'b0}}}); wire out_fifo_empty = out_fifo_wr_ptr_reg == out_fifo_rd_ptr_reg; +(* ram_style = "distributed" *) reg [AXIS_DATA_WIDTH-1:0] out_fifo_tdata[2**OUTPUT_FIFO_ADDR_WIDTH-1:0]; +(* ram_style = "distributed" *) reg [AXIS_KEEP_WIDTH-1:0] out_fifo_tkeep[2**OUTPUT_FIFO_ADDR_WIDTH-1:0]; +(* ram_style = "distributed" *) reg out_fifo_tlast[2**OUTPUT_FIFO_ADDR_WIDTH-1:0]; +(* ram_style = "distributed" *) reg [AXIS_ID_WIDTH-1:0] out_fifo_tid[2**OUTPUT_FIFO_ADDR_WIDTH-1:0]; +(* ram_style = "distributed" *) reg [AXIS_DEST_WIDTH-1:0] out_fifo_tdest[2**OUTPUT_FIFO_ADDR_WIDTH-1:0]; +(* ram_style = "distributed" *) reg [AXIS_USER_WIDTH-1:0] out_fifo_tuser[2**OUTPUT_FIFO_ADDR_WIDTH-1:0]; assign m_axis_read_data_tready_int = !out_fifo_half_full_reg; diff --git a/rtl/dma_if_pcie_us_wr.v b/rtl/dma_if_pcie_us_wr.v index 4261101..b14ae68 100644 --- a/rtl/dma_if_pcie_us_wr.v +++ b/rtl/dma_if_pcie_us_wr.v @@ -1205,9 +1205,13 @@ reg out_fifo_half_full_reg = 1'b0; wire out_fifo_full = out_fifo_wr_ptr_reg == (out_fifo_rd_ptr_reg ^ {1'b1, {OUTPUT_FIFO_ADDR_WIDTH{1'b0}}}); wire out_fifo_empty = out_fifo_wr_ptr_reg == out_fifo_rd_ptr_reg; +(* ram_style = "distributed" *) reg [AXIS_PCIE_DATA_WIDTH-1:0] out_fifo_tdata[2**OUTPUT_FIFO_ADDR_WIDTH-1:0]; +(* ram_style = "distributed" *) reg [AXIS_PCIE_KEEP_WIDTH-1:0] out_fifo_tkeep[2**OUTPUT_FIFO_ADDR_WIDTH-1:0]; +(* ram_style = "distributed" *) reg out_fifo_tlast[2**OUTPUT_FIFO_ADDR_WIDTH-1:0]; +(* ram_style = "distributed" *) reg [AXIS_PCIE_RQ_USER_WIDTH-1:0] out_fifo_tuser[2**OUTPUT_FIFO_ADDR_WIDTH-1:0]; assign m_axis_rq_tready_int = !out_fifo_half_full_reg;