Add PCIe tag manager
This commit is contained in:
Alex Forencich
parent
ff617532e0
commit
6e46c8e32d
168
rtl/pcie_tag_manager.v
Normal file
168
rtl/pcie_tag_manager.v
Normal file
@ -0,0 +1,168 @@
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/*
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Copyright (c) 2018 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* PCIe tag manager
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*/
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module pcie_tag_manager #
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(
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parameter PCIE_TAG_WIDTH = 8,
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parameter PCIE_TAG_COUNT = 256,
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parameter PCIE_EXT_TAG_ENABLE = 1
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)
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(
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input wire clk,
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input wire rst,
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/*
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* AXIS tag output
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*/
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output wire [PCIE_TAG_WIDTH-1:0] m_axis_tag,
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output wire m_axis_tag_valid,
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input wire m_axis_tag_ready,
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/*
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* AXIS tag output
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*/
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input wire [PCIE_TAG_WIDTH-1:0] s_axis_tag,
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input wire s_axis_tag_valid,
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/*
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* Configuration
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*/
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input wire ext_tag_enable,
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/*
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* Status
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*/
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output wire [PCIE_TAG_COUNT-1:0] active_tags
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);
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// parameter assertions
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initial begin
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if (PCIE_TAG_WIDTH < $clog2(PCIE_TAG_COUNT)) begin
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$error("Error: PCIe tag width insufficient for requested tag count");
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$finish;
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end
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if (PCIE_TAG_COUNT < 1 || PCIE_TAG_COUNT > 256) begin
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$error("Error: PCIe tag count must be between 1 and 256");
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$finish;
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end
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if (PCIE_TAG_COUNT > 32 && !PCIE_EXT_TAG_ENABLE) begin
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$warning("Warning: PCIe tag count set larger than 32, but extended tag support is disabled");
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end
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if (PCIE_TAG_COUNT <= 32 && PCIE_EXT_TAG_ENABLE) begin
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$warning("Warning: PCIe tag count set to 32 or less, but extended tag support is enabled");
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end
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end
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reg [PCIE_TAG_COUNT-1:0] tag_active_reg = {PCIE_TAG_COUNT{1'b0}}, tag_active_next;
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reg [PCIE_TAG_COUNT-1:0] tag_mask_reg = {PCIE_TAG_COUNT{1'b0}}, tag_mask_next;
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reg [PCIE_TAG_WIDTH-1:0] m_axis_tag_reg = {PCIE_TAG_WIDTH{1'b0}}, m_axis_tag_next;
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reg m_axis_tag_valid_reg = 1'b0, m_axis_tag_valid_next;
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assign m_axis_tag = m_axis_tag_reg;
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assign m_axis_tag_valid = m_axis_tag_valid_reg;
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assign active_tags = tag_active_reg;
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wire tag_valid;
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wire [PCIE_TAG_WIDTH-1:0] tag_index;
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priority_encoder #(
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.WIDTH(PCIE_TAG_COUNT),
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.LSB_PRIORITY("HIGH")
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)
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priority_encoder_inst (
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.input_unencoded(~tag_active_reg & (ext_tag_enable && PCIE_EXT_TAG_ENABLE ? {256{1'b1}} : {32{1'b1}})),
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.output_valid(tag_valid),
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.output_encoded(tag_index),
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.output_unencoded()
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);
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wire masked_tag_valid;
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wire [PCIE_TAG_WIDTH-1:0] masked_tag_index;
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priority_encoder #(
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.WIDTH(PCIE_TAG_COUNT),
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.LSB_PRIORITY("HIGH")
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)
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priority_encoder_masked (
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.input_unencoded(~tag_active_reg & tag_mask_reg & (ext_tag_enable && PCIE_EXT_TAG_ENABLE ? {256{1'b1}} : {32{1'b1}})),
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.output_valid(masked_tag_valid),
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.output_encoded(masked_tag_index),
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.output_unencoded()
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);
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always @* begin
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tag_active_next = tag_active_reg;
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tag_mask_next = tag_mask_reg;
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m_axis_tag_next = m_axis_tag_reg;
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m_axis_tag_valid_next = m_axis_tag_valid_reg && !m_axis_tag_ready;
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if (s_axis_tag_valid) begin
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tag_active_next[s_axis_tag] = 1'b0;
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end
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if (!m_axis_tag_valid || m_axis_tag_ready) begin
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if (tag_valid) begin
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if (masked_tag_valid) begin
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m_axis_tag_next = masked_tag_index;
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m_axis_tag_valid_next = 1'b1;
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tag_active_next[masked_tag_index] = 1'b1;
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tag_mask_next = {PCIE_TAG_COUNT{1'b1}} << (masked_tag_index + 1);
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end else begin
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m_axis_tag_next = tag_index;
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m_axis_tag_valid_next = 1'b1;
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tag_active_next[tag_index] = 1'b1;
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tag_mask_next = {PCIE_TAG_COUNT{1'b1}} << (tag_index + 1);
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end
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end
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end
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end
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always @(posedge clk) begin
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if (rst) begin
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tag_active_reg <= {PCIE_TAG_COUNT{1'b0}};
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tag_mask_reg <= {PCIE_TAG_COUNT{1'b0}};
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m_axis_tag_valid_reg <= 1'b0;
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end else begin
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tag_active_reg <= tag_active_next;
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tag_mask_reg <= tag_mask_next;
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m_axis_tag_valid_reg <= m_axis_tag_valid_next;
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end
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m_axis_tag_reg <= m_axis_tag_next;
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end
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endmodule
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209
tb/test_pcie_tag_manager.py
Executable file
209
tb/test_pcie_tag_manager.py
Executable file
@ -0,0 +1,209 @@
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#!/usr/bin/env python
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"""
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Copyright (c) 2018 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
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furnished to do so, subject to the following conditions:
|
||||
|
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
|
||||
|
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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"""
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from myhdl import *
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import os
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import axis_ep
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module = 'pcie_tag_manager'
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testbench = 'test_%s' % module
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srcs = []
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srcs.append("../rtl/%s.v" % module)
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srcs.append("../rtl/priority_encoder.v")
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srcs.append("%s.v" % testbench)
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src = ' '.join(srcs)
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build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
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def bench():
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# Parameters
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PCIE_TAG_WIDTH = 8
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PCIE_TAG_COUNT = 256
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PCIE_EXT_TAG_ENABLE = 1
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# Inputs
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clk = Signal(bool(0))
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rst = Signal(bool(0))
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current_test = Signal(intbv(0)[8:])
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m_axis_tag_ready = Signal(bool(0))
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s_axis_tag = Signal(intbv(0)[PCIE_TAG_WIDTH:])
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s_axis_tag_valid = Signal(bool(0))
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ext_tag_enable = Signal(bool(0))
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# Outputs
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m_axis_tag = Signal(intbv(0)[PCIE_TAG_WIDTH:])
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m_axis_tag_valid = Signal(bool(0))
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active_tags = Signal(intbv(0)[PCIE_TAG_COUNT:])
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# sources and sinks
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tag_sink_pause = Signal(bool(1))
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tag_source = axis_ep.AXIStreamSource()
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tag_source_logic = tag_source.create_logic(
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clk,
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rst,
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tdata=s_axis_tag,
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tvalid=s_axis_tag_valid,
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name='tag_source'
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)
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tag_sink = axis_ep.AXIStreamSink()
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tag_sink_logic = tag_sink.create_logic(
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clk,
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rst,
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tdata=m_axis_tag,
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tvalid=m_axis_tag_valid,
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tready=m_axis_tag_ready,
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pause=tag_sink_pause,
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name='tag_sink'
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)
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# DUT
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if os.system(build_cmd):
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raise Exception("Error running build command")
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dut = Cosimulation(
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"vvp -m myhdl %s.vvp -lxt2" % testbench,
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clk=clk,
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rst=rst,
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current_test=current_test,
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m_axis_tag=m_axis_tag,
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m_axis_tag_valid=m_axis_tag_valid,
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m_axis_tag_ready=m_axis_tag_ready,
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s_axis_tag=s_axis_tag,
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s_axis_tag_valid=s_axis_tag_valid,
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ext_tag_enable=ext_tag_enable,
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active_tags=active_tags
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)
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@always(delay(4))
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def clkgen():
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clk.next = not clk
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@instance
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def check():
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yield delay(100)
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yield clk.posedge
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rst.next = 1
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yield clk.posedge
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rst.next = 0
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yield clk.posedge
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yield delay(100)
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yield clk.posedge
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# testbench stimulus
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ext_tag_enable.next = 0
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yield clk.posedge
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print("test 1: activate all tags")
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current_test.next = 1
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tag_sink_pause.next = 0
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yield delay(300)
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tag_sink_pause.next = 1
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for k in range(32):
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assert tag_sink.recv().data[0] == k
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yield delay(100)
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yield clk.posedge
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print("test 2: return and reissue some tags")
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current_test.next = 2
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for k in [2, 4, 6, 8]:
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tag_source.send([k])
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tag_sink_pause.next = 0
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yield delay(100)
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tag_sink_pause.next = 1
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for k in [2, 4, 6, 8]:
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assert tag_sink.recv().data[0] == k
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yield delay(100)
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yield clk.posedge
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print("test 3: activate all extended tags")
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current_test.next = 3
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rst.next = 1
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ext_tag_enable.next = 1
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yield clk.posedge
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rst.next = 0
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tag_sink_pause.next = 0
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yield delay(2100)
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tag_sink_pause.next = 1
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for k in range(256):
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assert tag_sink.recv().data[0] == k
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yield delay(100)
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yield clk.posedge
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print("test 4: return and reissue some tags")
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current_test.next = 4
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for k in [10, 20, 30, 40, 50, 60]:
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tag_source.send([k])
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tag_sink_pause.next = 0
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yield delay(100)
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tag_sink_pause.next = 1
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for k in [10, 20, 30, 40, 50, 60]:
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assert tag_sink.recv().data[0] == k
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yield delay(100)
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raise StopSimulation
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return instances()
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def test_bench():
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sim = Simulation(bench())
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sim.run()
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if __name__ == '__main__':
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print("Running test...")
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test_bench()
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93
tb/test_pcie_tag_manager.v
Normal file
93
tb/test_pcie_tag_manager.v
Normal file
@ -0,0 +1,93 @@
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/*
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Copyright (c) 2018 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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||||
of this software and associated documentation files (the "Software"), to deal
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||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
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THE SOFTWARE.
|
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* Testbench for pcie_tag_manager
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*/
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module test_pcie_tag_manager;
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// Parameters
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parameter PCIE_TAG_WIDTH = 8;
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parameter PCIE_TAG_COUNT = 256;
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parameter PCIE_EXT_TAG_ENABLE = 1;
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// Inputs
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reg clk = 0;
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reg rst = 0;
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reg [7:0] current_test = 0;
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reg m_axis_tag_ready = 0;
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reg [PCIE_TAG_WIDTH-1:0] s_axis_tag = 0;
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reg s_axis_tag_valid = 0;
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reg ext_tag_enable = 0;
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// Outputs
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wire [PCIE_TAG_WIDTH-1:0] m_axis_tag;
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wire m_axis_tag_valid;
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wire [PCIE_TAG_COUNT-1:0] active_tags;
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initial begin
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// myhdl integration
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$from_myhdl(
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clk,
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rst,
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current_test,
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m_axis_tag_ready,
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s_axis_tag,
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s_axis_tag_valid,
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ext_tag_enable
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);
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$to_myhdl(
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m_axis_tag,
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m_axis_tag_valid,
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active_tags
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);
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// dump file
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$dumpfile("test_pcie_tag_manager.lxt");
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$dumpvars(0, test_pcie_tag_manager);
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end
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pcie_tag_manager #(
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.PCIE_TAG_WIDTH(PCIE_TAG_WIDTH),
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.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
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.PCIE_EXT_TAG_ENABLE(PCIE_EXT_TAG_ENABLE)
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)
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UUT (
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.clk(clk),
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.rst(rst),
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.m_axis_tag(m_axis_tag),
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.m_axis_tag_valid(m_axis_tag_valid),
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.m_axis_tag_ready(m_axis_tag_ready),
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.s_axis_tag(s_axis_tag),
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.s_axis_tag_valid(s_axis_tag_valid),
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.ext_tag_enable(ext_tag_enable),
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.active_tags(active_tags)
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);
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endmodule
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