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Remove unnecessary delays from testbenches

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This commit is contained in:
Alex Forencich 2021-02-24 13:50:45 -08:00
parent 40a191a06d
commit 6fb2eb6b4e
3 changed files with 0 additions and 9 deletions
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3
tb/dma_client_axis_sink/test_dma_client_axis_sink.py
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@ -144,9 +144,6 @@ async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_ins
assert int(status.tag) == cur_tag
assert int(status.id) == cur_tag
for k in range(10):
await RisingEdge(dut.clk)
tb.log.debug("%s", tb.dma_ram.hexdump_str((ram_addr & ~0xf)-16, (((ram_addr & 0xf)+length-1) & ~0xf)+48))
if len(test_data) <= len(test_data2):

3
tb/dma_if_pcie_us/test_dma_if_pcie_us.py
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@ -263,9 +263,6 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None):
assert int(status.tag) == cur_tag
for k in range(10):
await RisingEdge(dut.clk)
tb.log.debug("%s", tb.dma_ram.hexdump_str((ram_addr & ~0xf)-16, (((ram_addr & 0xf)+length-1) & ~0xf)+48, prefix="RAM "))
assert tb.dma_ram.read(ram_addr-8, len(test_data)+16) == b'\xaa'*8+test_data+b'\xaa'*8

3
tb/dma_if_pcie_us_rd/test_dma_if_pcie_us_rd.py
View File

@ -203,9 +203,6 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None):
assert int(status.tag) == cur_tag
for k in range(10):
await RisingEdge(dut.clk)
tb.log.debug("%s", tb.dma_ram.hexdump_str((ram_addr & ~0xf)-16, (((ram_addr & 0xf)+length-1) & ~0xf)+48, prefix="RAM "))
assert tb.dma_ram.read(ram_addr-8, len(test_data)+16) == b'\xaa'*8+test_data+b'\xaa'*8