Consolidate MSI capability objects
This commit is contained in:
Alex Forencich
parent
2b9e4ccb78
commit
76dccafe0e
145
tb/pcie.py
145
tb/pcie.py
@ -1207,18 +1207,22 @@ class PCIECapability(object):
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pass
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class MSI32Capability(object):
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class MSICapability(object):
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def __init__(self, *args, **kwargs):
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super(MSI32Capability, self).__init__(*args, **kwargs)
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super(MSICapability, self).__init__(*args, **kwargs)
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# MSI Capability Registes
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# MSI Capability Registers
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self.msi_enable = False
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self.msi_multiple_message_capable = 0
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self.msi_multiple_message_enable = 0
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self.msi_enable = False
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self.msi_64bit_address_capable = 0
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self.msi_per_vector_mask_capable = 0
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self.msi_message_address = 0
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self.msi_message_data = 0
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self.msi_mask_bits = 0
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self.msi_pending_bits = 0
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self.register_capability(MSI_CAP_ID, 3, self.read_msi_cap_register, self.write_msi_cap_register)
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self.register_capability(MSI_CAP_ID, 6, self.read_msi_cap_register, self.write_msi_cap_register)
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"""
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MSI Capability (32 bit)
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@ -1231,50 +1235,7 @@ class MSI32Capability(object):
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+---------------------------------+---------------------------------+
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| | Message Data | 2 0x08
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+---------------------------------+---------------------------------+
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"""
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def read_msi_cap_register(self, reg):
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if reg == 0:
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# Message control
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val = 0x00000000
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if self.msi_enable: val |= 1 << 16
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val |= (self.msi_multiple_message_capable & 0x7) << 17
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val |= (self.msi_multiple_message_enable & 0x7) << 20
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return val
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elif reg == 1:
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# Message address
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return self.msi_message_address & 0xfffffffc
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elif reg == 2:
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# Message data
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return self.msi_message_data & 0xffff
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def write_msi_cap_register(self, reg, write, offset=None):
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if reg == 0:
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# Message control
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if mask & 0x4: self.msi_enable = (data & 1 << 16 != 0)
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if mask & 0x4: self.msi_multiple_message_enable = (data >> 20) & 0x7
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elif reg == 1:
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# Message address
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self.msi_message_address = byte_mask_update(self.msi_message_address, mask, data) & 0xfffffffc
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elif reg == 2:
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# Message data
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self.msi_message_data = byte_mask_update(self.msi_message_data, mask & 0x3, data) & 0xffff
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class MSI64Capability(object):
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def __init__(self, *args, **kwargs):
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super(MSI64Capability, self).__init__(*args, **kwargs)
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# MSI Capability Registes
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self.msi_multiple_message_capable = 0
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self.msi_multiple_message_enable = 0
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self.msi_enable = False
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self.msi_message_address = 0
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self.msi_message_upper_address = 0
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self.msi_message_data = 0
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self.register_capability(MSI_CAP_ID, 4, self.read_msi_cap_register, self.write_msi_cap_register)
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"""
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MSI Capability (64 bit)
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31 0
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@ -1287,58 +1248,22 @@ class MSI64Capability(object):
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+---------------------------------+---------------------------------+
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| | Message Data | 3 0x0C
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+---------------------------------+---------------------------------+
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"""
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def read_msi_cap_register(self, reg):
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if reg == 0:
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# Message control
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val = 0x00800000
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if self.msi_enable: val |= 1 << 16
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val |= (self.msi_multiple_message_capable & 0x7) << 17
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val |= (self.msi_multiple_message_enable & 0x7) << 20
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return val
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elif reg == 1:
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# Message address
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return self.msi_message_address & 0xfffffffc
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elif reg == 2:
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# Message upper address
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return self.msi_message_upper_address & 0xffffffff
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elif reg == 3:
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# Message data
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return self.msi_message_data & 0xffff
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def write_msi_cap_register(self, reg, write, offset=None):
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if reg == 0:
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# Message control
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if mask & 0x4: self.msi_enable = (data & 1 << 16 != 0)
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if mask & 0x4: self.msi_multiple_message_enable = (data >> 20) & 0x7
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elif reg == 1:
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# Message address
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self.msi_message_address = byte_mask_update(self.msi_message_address, mask, data) & 0xfffffffc
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elif reg == 2:
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# Message upper address
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self.msi_message_upper_address = byte_mask_update(self.msi_message_upper_address, mask, data) & 0xffffffff
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elif reg == 3:
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# Message data
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self.msi_message_data = byte_mask_update(self.msi_message_data, mask & 0x3, data) & 0xffff
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MSI Capability (32 bit with per-vector masking)
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31 0
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+---------------------------------+----------------+----------------+
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| Message Control | Next Cap | Cap ID | 0 0x00
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+---------------------------------+----------------+----------------+
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| Message Address | 1 0x04
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+-------------------------------------------------------------------+
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| | Message Data | 2 0x08
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+---------------------------------+---------------------------------+
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| Mask Bits | 3 0x0C
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+-------------------------------------------------------------------+
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| Pending Bits | 4 0x10
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+-------------------------------------------------------------------+
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class MSI64MaskCapability(object):
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def __init__(self, *args, **kwargs):
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super(MSI64MaskCapability, self).__init__(*args, **kwargs)
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# MSI Capability Registes
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self.msi_enable = False
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self.msi_multiple_message_capable = 0
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self.msi_multiple_message_enable = 0
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self.msi_message_address = 0
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self.msi_message_upper_address = 0
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self.msi_message_data = 0
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self.msi_mask_bits = 0
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self.msi_pending_bits = 0
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self.register_capability(MSI_CAP_ID, 6, self.read_msi_cap_register, self.write_msi_cap_register)
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"""
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MSI Capability (64 bit with per-vector masking)
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31 0
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@ -1359,42 +1284,44 @@ class MSI64MaskCapability(object):
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def read_msi_cap_register(self, reg):
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if reg == 0:
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# Message control
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val = 0x01800000
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val = 0x00000000
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if self.msi_enable: val |= 1 << 16
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val |= (self.msi_multiple_message_capable & 0x7) << 17
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val |= (self.msi_multiple_message_enable & 0x7) << 20
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if self.msi_64bit_address_capable: val |= 1 << 23
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if self.msi_per_vector_mask_capable: val |= 1 << 24
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return val
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elif reg == 1:
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# Message address
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return self.msi_message_address & 0xfffffffc
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elif reg == 2:
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elif reg == 2 and self.msi_64bit_address_capable:
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# Message upper address
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return self.msi_message_upper_address & 0xffffffff
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elif reg == 3:
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return (self.msi_message_address >> 32) & 0xffffffff
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elif reg == (3 if self.msi_64bit_address_capable else 2):
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# Message data
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return self.msi_message_data & 0xffff
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elif reg == 4:
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elif reg == (4 if self.msi_64bit_address_capable else 3) and self.msi_per_vector_mask_capable:
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# Mask bits
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return self.msi_mask_bits & 0xffffffff
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elif reg == 5:
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elif reg == (5 if self.msi_64bit_address_capable else 4) and self.msi_per_vector_mask_capable:
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# Pending bits
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return self.msi_pending_bits & 0xffffffff
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def write_msi_cap_register(self, reg, write, offset=None):
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def write_msi_cap_register(self, reg, data, mask):
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if reg == 0:
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# Message control
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if mask & 0x4: self.msi_enable = (data & 1 << 16 != 0)
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if mask & 0x4: self.msi_multiple_message_enable = (data >> 20) & 0x7
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elif reg == 1:
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# Message address
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self.msi_message_address = byte_mask_update(self.msi_message_address, mask, data) & 0xfffffffc
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elif reg == 2:
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self.msi_message_address = byte_mask_update(self.msi_message_address, mask, data) & 0xfffffffffffffffc
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elif reg == 2 and self.msi_64bit_address_capable:
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# Message upper address
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self.msi_message_upper_address = byte_mask_update(self.msi_message_upper_address, mask, data) & 0xffffffff
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elif reg == 3:
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self.msi_message_address = byte_mask_update(self.msi_message_address, mask << 4, data << 32) & 0xfffffffffffffffc
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elif reg == (3 if self.msi_64bit_address_capable else 2):
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# Message data
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self.msi_message_data = byte_mask_update(self.msi_message_data, mask & 0x3, data) & 0xffff
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elif reg == 4:
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elif reg == (4 if self.msi_64bit_address_capable else 3) and self.msi_per_vector_mask_capable:
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# Mask bits
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self.msi_mask_bits = byte_mask_update(self.msi_mask_bits, mask, data) & 0xffffffff
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@ -643,10 +643,13 @@ class TLP_us(TLP):
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)
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class UltrascalePCIeFunction(Endpoint, MSI64MaskCapability, MSIXCapability):
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class UltrascalePCIeFunction(Endpoint, MSICapability, MSIXCapability):
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def __init__(self):
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super(UltrascalePCIeFunction, self).__init__()
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self.msi_64bit_address_capable = 1
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self.msi_per_vector_mask_capable = 0
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self.register_capability(PCIE_CAP_ID, offset=48)
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self.register_capability(MSIX_CAP_ID, offset=44)
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self.register_capability(PM_CAP_ID, offset=32)
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