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Add USPcieFrame intermediate format

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This commit is contained in:
Alex Forencich 2019-10-12 18:01:39 -07:00
parent 603a6e18e2
commit 9b5a5db4d1
7 changed files with 1084 additions and 272 deletions
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1181
tb/pcie_us.py
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File diff suppressed because it is too large Load Diff

20
tb/pcie_usp.py
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@ -80,10 +80,10 @@ class UltrascalePlusPCIe(Device):
self.config_space_enable = False
self.cq_source = axis_ep.AXIStreamSource()
self.cc_sink = axis_ep.AXIStreamSink()
self.rq_sink = axis_ep.AXIStreamSink()
self.rc_source = axis_ep.AXIStreamSource()
self.cq_source = CQSource()
self.cc_sink = CCSink()
self.rq_sink = RQSink()
self.rc_source = RCSource()
self.make_function()
@ -748,7 +748,7 @@ class UltrascalePlusPCIe(Device):
while self.cq_np_queue and self.cq_np_req_count > 0:
tlp = self.cq_np_queue.pop(0)
self.cq_np_req_count -= 1
self.cq_source.send(tlp.pack_us_cq(self.dw))
self.cq_source.send(tlp.pack_us_cq())
# handle new requests
while self.cq_queue:
@ -760,13 +760,13 @@ class UltrascalePlusPCIe(Device):
if self.cq_np_req_count > 0:
# have credit, can forward
self.cq_np_req_count -= 1
self.cq_source.send(tlp.pack_us_cq(self.dw))
self.cq_source.send(tlp.pack_us_cq())
else:
# no credits, put it in the queue
self.cq_np_queue.append(tlp)
else:
# posted request
self.cq_source.send(tlp.pack_us_cq(self.dw))
self.cq_source.send(tlp.pack_us_cq())
pcie_cq_np_req_count.next = self.cq_np_req_count
@ -774,7 +774,7 @@ class UltrascalePlusPCIe(Device):
while not self.cc_sink.empty():
pkt = self.cc_sink.recv()
tlp = TLP_us().unpack_us_cc(pkt, self.dw, self.enable_parity)
tlp = TLP_us().unpack_us_cc(pkt, self.enable_parity)
if not tlp.completer_id_enable:
tlp.completer_id = PcieId(self.bus_num, self.device_num, tlp.completer_id.function)
@ -786,7 +786,7 @@ class UltrascalePlusPCIe(Device):
while not self.rq_sink.empty():
pkt = self.rq_sink.recv()
tlp = TLP_us().unpack_us_rq(pkt, self.dw, self.enable_parity)
tlp = TLP_us().unpack_us_rq(pkt, self.enable_parity)
if not tlp.requester_id_enable:
tlp.requester_id = PcieId(self.bus_num, self.device_num, tlp.requester_id.function)
@ -805,7 +805,7 @@ class UltrascalePlusPCIe(Device):
# handle requester completions
while self.rc_queue:
tlp = self.rc_queue.pop(0)
self.rc_source.send(tlp.pack_us_rc(self.dw))
self.rc_source.send(tlp.pack_us_rc())
# transmit flow control
#pcie_tfc_nph_av

31
tb/test_pcie_us.py
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@ -27,7 +27,6 @@ from myhdl import *
import struct
import os
import axis_ep
import pcie
import pcie_us
@ -223,7 +222,7 @@ def bench():
pcie_perstn1_out=Signal(bool(0))
# sources and sinks
cq_sink = axis_ep.AXIStreamSink()
cq_sink = pcie_us.CQSink()
cq_sink_logic = cq_sink.create_logic(
user_clk,
@ -237,7 +236,7 @@ def bench():
name='cq_sink'
)
cc_source = axis_ep.AXIStreamSource()
cc_source = pcie_us.CCSource()
cc_source_logic = cc_source.create_logic(
user_clk,
@ -251,7 +250,7 @@ def bench():
name='cc_source'
)
rq_source = axis_ep.AXIStreamSource()
rq_source = pcie_us.RQSource()
rq_source_logic = rq_source.create_logic(
user_clk,
@ -265,7 +264,7 @@ def bench():
name='rq_source'
)
rc_sink = axis_ep.AXIStreamSink()
rc_sink = pcie_us.RCSink()
rc_sink_logic = rc_sink.create_logic(
user_clk,
@ -501,7 +500,7 @@ def bench():
if not cq_sink.empty():
pkt = cq_sink.recv()
tlp = pcie_us.TLP_us().unpack_us_cq(pkt, dw)
tlp = pcie_us.TLP_us().unpack_us_cq(pkt)
print(tlp)
@ -539,7 +538,7 @@ def bench():
cpl.byte_count = 4
cpl.length = 1
cc_source.send(cpl.pack_us_cc(dw))
cc_source.send(cpl.pack_us_cc())
elif (tlp.fmt_type == pcie.TLP_IO_WRITE):
print("IO write")
@ -569,7 +568,7 @@ def bench():
if start_offset is not None and offset != start_offset:
regions[region][addr+start_offset:addr+offset] = data[start_offset:offset]
cc_source.send(cpl.pack_us_cc(dw))
cc_source.send(cpl.pack_us_cc())
if (tlp.fmt_type == pcie.TLP_MEM_READ or tlp.fmt_type == pcie.TLP_MEM_READ_64):
print("Memory read")
@ -604,7 +603,7 @@ def bench():
cpl.set_data(data[offset+n:offset+n+byte_length])
print("Completion: %s" % (repr(cpl)))
cc_source.send(cpl.pack_us_cc(dw))
cc_source.send(cpl.pack_us_cc())
n += byte_length
addr += byte_length
@ -745,14 +744,14 @@ def bench():
current_tag = (current_tag % 31) + 1
rq_source.send(tlp.pack_us_rq(dw))
rq_source.send(tlp.pack_us_rq())
yield rc_sink.wait(100)
pkt = rc_sink.recv()
if not pkt:
raise Exception("Timeout")
cpl = pcie_us.TLP_us().unpack_us_rc(pkt, dw)
cpl = pcie_us.TLP_us().unpack_us_rc(pkt)
if cpl.status != pcie.CPL_STATUS_SC:
raise Exception("Unsuccessful completion")
@ -783,14 +782,14 @@ def bench():
current_tag = (current_tag % 31) + 1
rq_source.send(tlp.pack_us_rq(dw))
rq_source.send(tlp.pack_us_rq())
yield rc_sink.wait(100)
pkt = rc_sink.recv()
if not pkt:
raise Exception("Timeout")
cpl = pcie_us.TLP_us().unpack_us_rc(pkt, dw)
cpl = pcie_us.TLP_us().unpack_us_rc(pkt)
if cpl.status != pcie.CPL_STATUS_SC:
raise Exception("Unsuccessful completion")
@ -831,7 +830,7 @@ def bench():
current_tag = (current_tag % 31) + 1
rq_source.send(tlp.pack_us_rq(dw))
rq_source.send(tlp.pack_us_rq())
n += byte_length
addr += byte_length
@ -865,7 +864,7 @@ def bench():
current_tag = (current_tag % 31) + 1
rq_source.send(tlp.pack_us_rq(dw))
rq_source.send(tlp.pack_us_rq())
m = 0
@ -876,7 +875,7 @@ def bench():
if not pkt:
raise Exception("Timeout")
cpl = pcie_us.TLP_us().unpack_us_rc(pkt, dw)
cpl = pcie_us.TLP_us().unpack_us_rc(pkt)
if cpl.status != pcie.CPL_STATUS_SC:
raise Exception("Unsuccessful completion")

31
tb/test_pcie_us_axil_master_128.py
View File

@ -26,7 +26,6 @@ THE SOFTWARE.
from myhdl import *
import os
import axis_ep
import axil
import pcie_us
@ -98,7 +97,7 @@ def bench():
status_error_uncor = Signal(bool(0))
# sources and sinks
cq_source = axis_ep.AXIStreamSource()
cq_source = pcie_us.CQSource()
cq_source_logic = cq_source.create_logic(
clk,
@ -112,7 +111,7 @@ def bench():
name='cq_source'
)
cc_sink = axis_ep.AXIStreamSink()
cc_sink = pcie_us.CCSink()
cc_sink_logic = cc_sink.create_logic(
clk,
@ -258,7 +257,7 @@ def bench():
tlp.set_be_data(0x0000, b'\x11\x22\x33\x44')
tlp.address = 0x0000
cq_source.send(tlp.pack_us_cq(AXIS_PCIE_DATA_WIDTH))
cq_source.send(tlp.pack_us_cq())
yield delay(100)
@ -287,12 +286,12 @@ def bench():
tlp.set_be_data(0x0000, b'\x11\x22\x33\x44')
tlp.address = 0x0000
cq_source.send(tlp.pack_us_cq(AXIS_PCIE_DATA_WIDTH))
cq_source.send(tlp.pack_us_cq())
yield cc_sink.wait(500)
pkt = cc_sink.recv()
rx_tlp = pcie_us.TLP_us().unpack_us_cc(pkt, AXIS_PCIE_DATA_WIDTH)
rx_tlp = pcie_us.TLP_us().unpack_us_cc(pkt)
print(rx_tlp)
@ -326,12 +325,12 @@ def bench():
tlp.set_be(0x0000, 4)
tlp.address = 0x0000
cq_source.send(tlp.pack_us_cq(AXIS_PCIE_DATA_WIDTH))
cq_source.send(tlp.pack_us_cq())
yield cc_sink.wait(500)
pkt = cc_sink.recv()
rx_tlp = pcie_us.TLP_us().unpack_us_cc(pkt, AXIS_PCIE_DATA_WIDTH)
rx_tlp = pcie_us.TLP_us().unpack_us_cc(pkt)
print(rx_tlp)
@ -364,12 +363,12 @@ def bench():
tlp.set_be(0x0000, 4)
tlp.address = 0x0000
cq_source.send(tlp.pack_us_cq(AXIS_PCIE_DATA_WIDTH))
cq_source.send(tlp.pack_us_cq())
yield cc_sink.wait(500)
pkt = cc_sink.recv()
rx_tlp = pcie_us.TLP_us().unpack_us_cc(pkt, AXIS_PCIE_DATA_WIDTH)
rx_tlp = pcie_us.TLP_us().unpack_us_cc(pkt)
print(rx_tlp)
@ -405,7 +404,7 @@ def bench():
tlp.set_be_data(256*(16*offset+length)+offset, b'\x11\x22\x33\x44'[0:length])
tlp.address = 256*(16*offset+length)+offset
cq_source.send(tlp.pack_us_cq(AXIS_PCIE_DATA_WIDTH))
cq_source.send(tlp.pack_us_cq())
yield delay(100)
@ -439,12 +438,12 @@ def bench():
tlp.set_be(256*(16*offset+length)+offset, length)
tlp.address = 256*(16*offset+length)+offset
cq_source.send(tlp.pack_us_cq(AXIS_PCIE_DATA_WIDTH))
cq_source.send(tlp.pack_us_cq())
yield cc_sink.wait(500)
pkt = cc_sink.recv()
rx_tlp = pcie_us.TLP_us().unpack_us_cc(pkt, AXIS_PCIE_DATA_WIDTH)
rx_tlp = pcie_us.TLP_us().unpack_us_cc(pkt)
print(rx_tlp)
@ -476,7 +475,7 @@ def bench():
tlp.set_be_data(0x0000, bytearray(range(64)))
tlp.address = 0x0000
cq_source.send(tlp.pack_us_cq(AXIS_PCIE_DATA_WIDTH))
cq_source.send(tlp.pack_us_cq())
yield delay(100)
@ -501,12 +500,12 @@ def bench():
tlp.set_be(0x0000, 64)
tlp.address = 0x0000
cq_source.send(tlp.pack_us_cq(AXIS_PCIE_DATA_WIDTH))
cq_source.send(tlp.pack_us_cq())
yield cc_sink.wait(500)
pkt = cc_sink.recv()
rx_tlp = pcie_us.TLP_us().unpack_us_cc(pkt, AXIS_PCIE_DATA_WIDTH)
rx_tlp = pcie_us.TLP_us().unpack_us_cc(pkt)
print(rx_tlp)

31
tb/test_pcie_us_axil_master_256.py
View File

@ -26,7 +26,6 @@ THE SOFTWARE.
from myhdl import *
import os
import axis_ep
import axil
import pcie_us
@ -98,7 +97,7 @@ def bench():
status_error_uncor = Signal(bool(0))
# sources and sinks
cq_source = axis_ep.AXIStreamSource()
cq_source = pcie_us.CQSource()
cq_source_logic = cq_source.create_logic(
clk,
@ -112,7 +111,7 @@ def bench():
name='cq_source'
)
cc_sink = axis_ep.AXIStreamSink()
cc_sink = pcie_us.CCSink()
cc_sink_logic = cc_sink.create_logic(
clk,
@ -258,7 +257,7 @@ def bench():
tlp.set_be_data(0x0000, b'\x11\x22\x33\x44')
tlp.address = 0x0000
cq_source.send(tlp.pack_us_cq(AXIS_PCIE_DATA_WIDTH))
cq_source.send(tlp.pack_us_cq())
yield delay(100)
@ -287,12 +286,12 @@ def bench():
tlp.set_be_data(0x0000, b'\x11\x22\x33\x44')
tlp.address = 0x0000
cq_source.send(tlp.pack_us_cq(AXIS_PCIE_DATA_WIDTH))
cq_source.send(tlp.pack_us_cq())
yield cc_sink.wait(500)
pkt = cc_sink.recv()
rx_tlp = pcie_us.TLP_us().unpack_us_cc(pkt, AXIS_PCIE_DATA_WIDTH)
rx_tlp = pcie_us.TLP_us().unpack_us_cc(pkt)
print(rx_tlp)
@ -326,12 +325,12 @@ def bench():
tlp.set_be(0x0000, 4)
tlp.address = 0x0000
cq_source.send(tlp.pack_us_cq(AXIS_PCIE_DATA_WIDTH))
cq_source.send(tlp.pack_us_cq())
yield cc_sink.wait(500)
pkt = cc_sink.recv()
rx_tlp = pcie_us.TLP_us().unpack_us_cc(pkt, AXIS_PCIE_DATA_WIDTH)
rx_tlp = pcie_us.TLP_us().unpack_us_cc(pkt)
print(rx_tlp)
@ -364,12 +363,12 @@ def bench():
tlp.set_be(0x0000, 4)
tlp.address = 0x0000
cq_source.send(tlp.pack_us_cq(AXIS_PCIE_DATA_WIDTH))
cq_source.send(tlp.pack_us_cq())
yield cc_sink.wait(500)
pkt = cc_sink.recv()
rx_tlp = pcie_us.TLP_us().unpack_us_cc(pkt, AXIS_PCIE_DATA_WIDTH)
rx_tlp = pcie_us.TLP_us().unpack_us_cc(pkt)
print(rx_tlp)
@ -405,7 +404,7 @@ def bench():
tlp.set_be_data(256*(16*offset+length)+offset, b'\x11\x22\x33\x44'[0:length])
tlp.address = 256*(16*offset+length)+offset
cq_source.send(tlp.pack_us_cq(AXIS_PCIE_DATA_WIDTH))
cq_source.send(tlp.pack_us_cq())
yield delay(100)
@ -439,12 +438,12 @@ def bench():
tlp.set_be(256*(16*offset+length)+offset, length)
tlp.address = 256*(16*offset+length)+offset
cq_source.send(tlp.pack_us_cq(AXIS_PCIE_DATA_WIDTH))
cq_source.send(tlp.pack_us_cq())
yield cc_sink.wait(500)
pkt = cc_sink.recv()
rx_tlp = pcie_us.TLP_us().unpack_us_cc(pkt, AXIS_PCIE_DATA_WIDTH)
rx_tlp = pcie_us.TLP_us().unpack_us_cc(pkt)
print(rx_tlp)
@ -476,7 +475,7 @@ def bench():
tlp.set_be_data(0x0000, bytearray(range(64)))
tlp.address = 0x0000
cq_source.send(tlp.pack_us_cq(AXIS_PCIE_DATA_WIDTH))
cq_source.send(tlp.pack_us_cq())
yield delay(100)
@ -501,12 +500,12 @@ def bench():
tlp.set_be(0x0000, 64)
tlp.address = 0x0000
cq_source.send(tlp.pack_us_cq(AXIS_PCIE_DATA_WIDTH))
cq_source.send(tlp.pack_us_cq())
yield cc_sink.wait(500)
pkt = cc_sink.recv()
rx_tlp = pcie_us.TLP_us().unpack_us_cc(pkt, AXIS_PCIE_DATA_WIDTH)
rx_tlp = pcie_us.TLP_us().unpack_us_cc(pkt)
print(rx_tlp)

31
tb/test_pcie_us_axil_master_64.py
View File

@ -26,7 +26,6 @@ THE SOFTWARE.
from myhdl import *
import os
import axis_ep
import axil
import pcie_us
@ -98,7 +97,7 @@ def bench():
status_error_uncor = Signal(bool(0))
# sources and sinks
cq_source = axis_ep.AXIStreamSource()
cq_source = pcie_us.CQSource()
cq_source_logic = cq_source.create_logic(
clk,
@ -112,7 +111,7 @@ def bench():
name='cq_source'
)
cc_sink = axis_ep.AXIStreamSink()
cc_sink = pcie_us.CCSink()
cc_sink_logic = cc_sink.create_logic(
clk,
@ -258,7 +257,7 @@ def bench():
tlp.set_be_data(0x0000, b'\x11\x22\x33\x44')
tlp.address = 0x0000
cq_source.send(tlp.pack_us_cq(AXIS_PCIE_DATA_WIDTH))
cq_source.send(tlp.pack_us_cq())
yield delay(100)
@ -287,12 +286,12 @@ def bench():
tlp.set_be_data(0x0000, b'\x11\x22\x33\x44')
tlp.address = 0x0000
cq_source.send(tlp.pack_us_cq(AXIS_PCIE_DATA_WIDTH))
cq_source.send(tlp.pack_us_cq())
yield cc_sink.wait(500)
pkt = cc_sink.recv()
rx_tlp = pcie_us.TLP_us().unpack_us_cc(pkt, AXIS_PCIE_DATA_WIDTH)
rx_tlp = pcie_us.TLP_us().unpack_us_cc(pkt)
print(rx_tlp)
@ -326,12 +325,12 @@ def bench():
tlp.set_be(0x0000, 4)
tlp.address = 0x0000
cq_source.send(tlp.pack_us_cq(AXIS_PCIE_DATA_WIDTH))
cq_source.send(tlp.pack_us_cq())
yield cc_sink.wait(500)
pkt = cc_sink.recv()
rx_tlp = pcie_us.TLP_us().unpack_us_cc(pkt, AXIS_PCIE_DATA_WIDTH)
rx_tlp = pcie_us.TLP_us().unpack_us_cc(pkt)
print(rx_tlp)
@ -364,12 +363,12 @@ def bench():
tlp.set_be(0x0000, 4)
tlp.address = 0x0000
cq_source.send(tlp.pack_us_cq(AXIS_PCIE_DATA_WIDTH))
cq_source.send(tlp.pack_us_cq())
yield cc_sink.wait(500)
pkt = cc_sink.recv()
rx_tlp = pcie_us.TLP_us().unpack_us_cc(pkt, AXIS_PCIE_DATA_WIDTH)
rx_tlp = pcie_us.TLP_us().unpack_us_cc(pkt)
print(rx_tlp)
@ -405,7 +404,7 @@ def bench():
tlp.set_be_data(256*(16*offset+length)+offset, b'\x11\x22\x33\x44'[0:length])
tlp.address = 256*(16*offset+length)+offset
cq_source.send(tlp.pack_us_cq(AXIS_PCIE_DATA_WIDTH))
cq_source.send(tlp.pack_us_cq())
yield delay(100)
@ -439,12 +438,12 @@ def bench():
tlp.set_be(256*(16*offset+length)+offset, length)
tlp.address = 256*(16*offset+length)+offset
cq_source.send(tlp.pack_us_cq(AXIS_PCIE_DATA_WIDTH))
cq_source.send(tlp.pack_us_cq())
yield cc_sink.wait(500)
pkt = cc_sink.recv()
rx_tlp = pcie_us.TLP_us().unpack_us_cc(pkt, AXIS_PCIE_DATA_WIDTH)
rx_tlp = pcie_us.TLP_us().unpack_us_cc(pkt)
print(rx_tlp)
@ -476,7 +475,7 @@ def bench():
tlp.set_be_data(0x0000, bytearray(range(64)))
tlp.address = 0x0000
cq_source.send(tlp.pack_us_cq(AXIS_PCIE_DATA_WIDTH))
cq_source.send(tlp.pack_us_cq())
yield delay(100)
@ -501,12 +500,12 @@ def bench():
tlp.set_be(0x0000, 64)
tlp.address = 0x0000
cq_source.send(tlp.pack_us_cq(AXIS_PCIE_DATA_WIDTH))
cq_source.send(tlp.pack_us_cq())
yield cc_sink.wait(500)
pkt = cc_sink.recv()
rx_tlp = pcie_us.TLP_us().unpack_us_cc(pkt, AXIS_PCIE_DATA_WIDTH)
rx_tlp = pcie_us.TLP_us().unpack_us_cc(pkt)
print(rx_tlp)

31
tb/test_pcie_usp.py
View File

@ -27,7 +27,6 @@ from myhdl import *
import struct
import os
import axis_ep
import pcie
import pcie_usp
@ -221,7 +220,7 @@ def bench():
phy_rdy_out=Signal(bool(0))
# sources and sinks
cq_sink = axis_ep.AXIStreamSink()
cq_sink = pcie_usp.CQSink()
cq_sink_logic = cq_sink.create_logic(
user_clk,
@ -235,7 +234,7 @@ def bench():
name='cq_sink'
)
cc_source = axis_ep.AXIStreamSource()
cc_source = pcie_usp.CCSource()
cc_source_logic = cc_source.create_logic(
user_clk,
@ -249,7 +248,7 @@ def bench():
name='cc_source'
)
rq_source = axis_ep.AXIStreamSource()
rq_source = pcie_usp.RQSource()
rq_source_logic = rq_source.create_logic(
user_clk,
@ -263,7 +262,7 @@ def bench():
name='rq_source'
)
rc_sink = axis_ep.AXIStreamSink()
rc_sink = pcie_usp.RCSink()
rc_sink_logic = rc_sink.create_logic(
user_clk,
@ -497,7 +496,7 @@ def bench():
if not cq_sink.empty():
pkt = cq_sink.recv()
tlp = pcie_usp.TLP_us().unpack_us_cq(pkt, dw)
tlp = pcie_usp.TLP_us().unpack_us_cq(pkt)
print(tlp)
@ -535,7 +534,7 @@ def bench():
cpl.byte_count = 4
cpl.length = 1
cc_source.send(cpl.pack_us_cc(dw))
cc_source.send(cpl.pack_us_cc())
elif (tlp.fmt_type == pcie.TLP_IO_WRITE):
print("IO write")
@ -565,7 +564,7 @@ def bench():
if start_offset is not None and offset != start_offset:
regions[region][addr+start_offset:addr+offset] = data[start_offset:offset]
cc_source.send(cpl.pack_us_cc(dw))
cc_source.send(cpl.pack_us_cc())
if (tlp.fmt_type == pcie.TLP_MEM_READ or tlp.fmt_type == pcie.TLP_MEM_READ_64):
print("Memory read")
@ -600,7 +599,7 @@ def bench():
cpl.set_data(data[offset+n:offset+n+byte_length])
print("Completion: %s" % (repr(cpl)))
cc_source.send(cpl.pack_us_cc(dw))
cc_source.send(cpl.pack_us_cc())
n += byte_length
addr += byte_length
@ -741,14 +740,14 @@ def bench():
current_tag = (current_tag % 31) + 1
rq_source.send(tlp.pack_us_rq(dw))
rq_source.send(tlp.pack_us_rq())
yield rc_sink.wait(100)
pkt = rc_sink.recv()
if not pkt:
raise Exception("Timeout")
cpl = pcie_usp.TLP_us().unpack_us_rc(pkt, dw)
cpl = pcie_usp.TLP_us().unpack_us_rc(pkt)
if cpl.status != pcie.CPL_STATUS_SC:
raise Exception("Unsuccessful completion")
@ -779,14 +778,14 @@ def bench():
current_tag = (current_tag % 31) + 1
rq_source.send(tlp.pack_us_rq(dw))
rq_source.send(tlp.pack_us_rq())
yield rc_sink.wait(100)
pkt = rc_sink.recv()
if not pkt:
raise Exception("Timeout")
cpl = pcie_usp.TLP_us().unpack_us_rc(pkt, dw)
cpl = pcie_usp.TLP_us().unpack_us_rc(pkt)
if cpl.status != pcie.CPL_STATUS_SC:
raise Exception("Unsuccessful completion")
@ -827,7 +826,7 @@ def bench():
current_tag = (current_tag % 31) + 1
rq_source.send(tlp.pack_us_rq(dw))
rq_source.send(tlp.pack_us_rq())
n += byte_length
addr += byte_length
@ -861,7 +860,7 @@ def bench():
current_tag = (current_tag % 31) + 1
rq_source.send(tlp.pack_us_rq(dw))
rq_source.send(tlp.pack_us_rq())
m = 0
@ -872,7 +871,7 @@ def bench():
if not pkt:
raise Exception("Timeout")
cpl = pcie_usp.TLP_us().unpack_us_rc(pkt, dw)
cpl = pcie_usp.TLP_us().unpack_us_rc(pkt)
if cpl.status != pcie.CPL_STATUS_SC:
raise Exception("Unsuccessful completion")