From 9b5a5db4d10d56539ab8fb1c9bc3709a80c707ba Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Sat, 12 Oct 2019 18:01:39 -0700 Subject: [PATCH] Add USPcieFrame intermediate format --- tb/pcie_us.py | 1181 +++++++++++++++++++++++----- tb/pcie_usp.py | 20 +- tb/test_pcie_us.py | 31 +- tb/test_pcie_us_axil_master_128.py | 31 +- tb/test_pcie_us_axil_master_256.py | 31 +- tb/test_pcie_us_axil_master_64.py | 31 +- tb/test_pcie_usp.py | 31 +- 7 files changed, 1084 insertions(+), 272 deletions(-) diff --git a/tb/pcie_us.py b/tb/pcie_us.py index e047ded..571f79f 100644 --- a/tb/pcie_us.py +++ b/tb/pcie_us.py @@ -26,7 +26,6 @@ import math import struct from myhdl import * -import axis_ep from pcie import * @@ -68,6 +67,52 @@ def dword_parity(d): return p +class USPcieFrame(object): + def __init__(self, frame=None): + self.data = [] + self.byte_en = [] + self.parity = [] + self.first_be = 0 + self.last_be = 0 + self.discontinue = False + + if isinstance(frame, USPcieFrame): + self.data = list(frame.data) + self.byte_en = list(frame.byte_en) + self.parity = list(frame.parity) + self.first_be = frame.first_be + self.last_be = frame.last_be + self.discontinue = frame.discontinue + + def update_parity(self): + self.parity = [dword_parity(d) ^ 0xf for d in self.data] + + def check_parity(self): + return self.parity == [dword_parity(d) ^ 0xf for d in self.data] + + def __eq__(self, other): + if isinstance(other, TLP_us): + return ( + self.data == other.data and + self.byte_en == other.byte_en and + self.parity == other.parity and + self.first_be == other.first_be and + self.last_be == other.last_be and + self.discontinue == other.discontinue + ) + return False + + def __repr__(self): + return ( + ('USPcieFrame(data=[{}], '.format(', '.join('{:#010x}'.format(x) for x in self.data))) + + ('byte_en=[{}], '.format(', '.join(hex(x) for x in self.byte_en))) + + ('parity=[{}], '.format(', '.join(hex(x) for x in self.parity))) + + ('first_be={:#x}, '.format(self.first_be)) + + ('last_be={:#x}, '.format(self.last_be)) + + ('discontinue={})'.format(self.discontinue)) + ) + + class TLP_us(TLP): def __init__(self, tlp=None): super(TLP_us, self).__init__(tlp) @@ -86,8 +131,8 @@ class TLP_us(TLP): self.discontinue = tlp.discontinue self.error_code = tlp.error_code - def pack_us_cq(self, dw): - pkt = axis_ep.AXIStreamFrame([]) + def pack_us_cq(self): + pkt = USPcieFrame() if (self.fmt_type == TLP_IO_READ or self.fmt_type == TLP_IO_WRITE or self.fmt_type == TLP_MEM_READ or self.fmt_type == TLP_MEM_READ_64 or @@ -125,52 +170,32 @@ class TLP_us(TLP): l |= (self.attr & 0x7) << 28 pkt.data.append(l) + pkt.first_be = self.first_be + pkt.last_be = self.last_be + + pkt.discontinue = self.discontinue + # payload data pkt.data += self.data # compute byte enables - byte_en = [0]*4 + pkt.byte_en = [0]*4 if len(self.data) >= 1: - byte_en += [self.first_be] + pkt.byte_en += [self.first_be] if len(self.data) > 2: - byte_en += [0xf] * (len(self.data)-2) + pkt.byte_en += [0xf] * (len(self.data)-2) if len(self.data) > 1: - byte_en += [self.last_be] + pkt.byte_en += [self.last_be] # compute parity - parity = [dword_parity(d) ^ 0xf for d in pkt.data] - - # assemble sideband signal - pkt.user = [] - - for k in range(0, len(pkt.data), int(dw/32)): - u = 0 - - for l in range(int(dw/32)): - if k+l < len(byte_en): - u |= byte_en[k+l] << l*4+8 - u |= parity[k+l] << l*4+53 - else: - u |= 0xf<< l*4+53 - - if k == 0: - u |= (self.first_be & 0xf) - u |= (self.last_be & 0xf) << 4 - u |= 1 << 40 # SOP - - # TODO tph - - pkt.user.append(u) - - # TODO discontinue? - + pkt.update_parity() else: raise Exception("Invalid packet type for interface") return pkt - def unpack_us_cq(self, pkt, dw, check_parity=False): + def unpack_us_cq(self, pkt, check_parity=False): req_type = (pkt.data[2] >> 11) & 0xf if req_type == REQ_MEM_READ: @@ -211,8 +236,10 @@ class TLP_us(TLP): self.bar_id = (pkt.data[3] >> 16) & 7 self.bar_aperture = (pkt.data[3] >> 19) & 0x3f - self.first_be = pkt.user[0] & 0xf - self.last_be = (pkt.user[0] >> 4) & 0xf + self.first_be = pkt.first_be + self.last_be = pkt.last_be + + self.discontinue = pkt.discontinue self.data = pkt.data[4:] @@ -226,23 +253,17 @@ class TLP_us(TLP): if len(self.data) > 1: byte_en += [self.last_be] - # compute parity - parity = [dword_parity(d) ^ 0xf for d in pkt.data] + # check byte enables + assert byte_en == pkt.byte_en - # check sideband components - assert pkt.user[0] & (1 << 40) # SOP - - for k in range(0, len(pkt.data), int(dw/32)): - for l in range(int(dw/32)): - if k+l < len(byte_en): - assert (pkt.user[int(k/(dw/32))] >> l*4+8) & 0xf == byte_en[k+l] - if check_parity: - assert (pkt.user[int(k/(dw/32))] >> l*4+53) & 0xf == parity[k+l] + # check parity + if check_parity: + assert pkt.check_parity() return self - def pack_us_cc(self, dw): - pkt = axis_ep.AXIStreamFrame([]) + def pack_us_cc(self): + pkt = USPcieFrame() if (self.fmt_type == TLP_CPL or self.fmt_type == TLP_CPL_DATA or self.fmt_type == TLP_CPL_LOCKED or self.fmt_type == TLP_CPL_LOCKED_DATA): @@ -267,35 +288,19 @@ class TLP_us(TLP): l |= (self.attr & 0x7) << 28 pkt.data.append(l) + pkt.discontinue = self.discontinue + # payload data pkt.data += self.data # compute parity - parity = [dword_parity(d) ^ 0xf for d in pkt.data] - - # assemble sideband signal - pkt.user = [] - - for k in range(0, len(pkt.data), int(dw/32)): - u = 0 - - if self.discontinue: - u |= 1 - - for l in range(int(dw/32)): - if k+l < len(parity): - u |= parity[k+l] << l*4+1 - else: - u |= 0xf << l*4+1 - - pkt.user.append(u) - + pkt.update_parity() else: raise Exception("Invalid packet type for interface") return pkt - def unpack_us_cc(self, pkt, dw, check_parity=False): + def unpack_us_cc(self, pkt, check_parity=False): self.fmt_type = TLP_CPL self.lower_address = pkt.data[0] & 0x7f @@ -315,25 +320,19 @@ class TLP_us(TLP): self.tc = (pkt.data[2] >> 25) & 0x7 self.attr = (pkt.data[2] >> 28) & 0x7 + self.discontinue = pkt.discontinue + if self.length > 0: self.data = pkt.data[3:3+self.length] - # compute parity - parity = [dword_parity(d) ^ 0xf for d in pkt.data] - - # check sideband components - for k in range(0, len(pkt.data), int(dw/32)): - if pkt.user[int(k/(dw/32))] & 1: - self.discontinue = True - for l in range(int(dw/32)): - if k+l < len(parity): - if check_parity: - assert (pkt.user[int(k/(dw/32))] >> l*4+1) & 0xf == parity[k+l] + # check parity + if check_parity: + assert pkt.check_parity() return self - def pack_us_rq(self, dw): - pkt = axis_ep.AXIStreamFrame([]) + def pack_us_rq(self): + pkt = USPcieFrame() if (self.fmt_type == TLP_IO_READ or self.fmt_type == TLP_IO_WRITE or self.fmt_type == TLP_MEM_READ or self.fmt_type == TLP_MEM_READ_64 or @@ -390,44 +389,22 @@ class TLP_us(TLP): # TODO force ecrc pkt.data.append(l) + pkt.first_be = self.first_be + pkt.last_be = self.last_be + + pkt.discontinue = self.discontinue + # payload data pkt.data += self.data # compute parity - parity = [dword_parity(d) ^ 0xf for d in pkt.data] - - # assemble sideband signal - pkt.user = [] - - for k in range(0, len(pkt.data), int(dw/32)): - u = 0 - - if self.discontinue: - u |= 1 << 11 - - for l in range(int(dw/32)): - if k+l < len(parity): - u |= parity[k+l] << l*4+28 - else: - u |= 0xf << l*4+28 - - if k == 0: - u |= (self.first_be & 0xf) - u |= (self.last_be & 0xf) << 4 - - # TODO seq_num - # TODO tph - - # TODO addr_offset - - pkt.user.append(u) - + pkt.update_parity() else: raise Exception("Invalid packet type for interface") return pkt - def unpack_us_rq(self, pkt, dw, check_parity=False): + def unpack_us_rq(self, pkt, check_parity=False): req_type = (pkt.data[2] >> 11) & 0xf if req_type == REQ_MEM_READ: @@ -479,29 +456,23 @@ class TLP_us(TLP): self.completer_id = PcieId.from_int(pkt.data[3] >> 8) self.requester_id_enable = pkt.data[3] >> 24 & 1 != 0 - self.first_be = pkt.user[0] & 0xf - self.last_be = (pkt.user[0] >> 4) & 0xf + self.first_be = pkt.first_be + self.last_be = pkt.last_be + + self.discontinue = pkt.discontinue self.data = pkt.data[4:] - # compute parity - parity = [dword_parity(d) ^ 0xf for d in pkt.data] - - # check sideband components - for k in range(0, len(pkt.data), int(dw/32)): - if pkt.user[int(k/(dw/32))] & (1 << 11): - self.discontinue = True - for l in range(int(dw/32)): - if k+l < len(parity): - if check_parity: - assert (pkt.user[int(k/(dw/32))] >> l*4+28) & 0xf == parity[k+l] + # check parity + if check_parity: + assert pkt.check_parity() else: raise Exception("TODO") return self - def pack_us_rc(self, dw): - pkt = axis_ep.AXIStreamFrame([]) + def pack_us_rc(self): + pkt = USPcieFrame() if (self.fmt_type == TLP_CPL or self.fmt_type == TLP_CPL_DATA or self.fmt_type == TLP_CPL_LOCKED or self.fmt_type == TLP_CPL_LOCKED_DATA): @@ -524,64 +495,39 @@ class TLP_us(TLP): l |= (self.attr & 0x7) << 28 pkt.data.append(l) + pkt.discontinue = self.discontinue + # payload data pkt.data += self.data # compute byte enables - byte_en = [0]*3 + pkt.byte_en = [0]*3 first_be = (0xf << (self.lower_address&3)) & 0xf if self.byte_count+(self.lower_address&3) > self.length*4: last_be = 0xf else: - last_be = 0xf >> ((self.byte_count+self.lower_address)&3) + last_be = 0xf >> ((4-self.byte_count-self.lower_address)&3) if len(self.data) == 1: first_be = first_be & last_be last_be = 0 if len(self.data) >= 1: - byte_en += [first_be] + pkt.byte_en += [first_be] if len(self.data) > 2: - byte_en += [0xf] * (len(self.data)-2) + pkt.byte_en += [0xf] * (len(self.data)-2) if len(self.data) > 1: - byte_en += [last_be] + pkt.byte_en += [last_be] # compute parity - parity = [dword_parity(d) ^ 0xf for d in pkt.data] - - # assemble sideband signal - pkt.user = [] - - for k in range(0, len(pkt.data), int(dw/32)): - u = 0 - - for l in range(int(dw/32)): - if k+l < len(byte_en): - u |= byte_en[k+l] << l*4 - u |= parity[k+l] << l*4+43 - else: - u |= 0xf << l*4+43 - - if k == 0: - u |= 1 << 32 # is_sof_0 - eof = 0 - if k+int(dw/32) > len(byte_en): - eof = 1 | ((len(byte_en)-1) % int(dw/32)) << 1 - u |= eof << 34 # is_eof_0 - - # TODO is_sof_1, is_eof_1 (straddle) - - pkt.user.append(u) - - # TODO discontinue - + pkt.update_parity() else: raise Exception("Invalid packet type for interface") return pkt - def unpack_us_rc(self, pkt, dw, check_parity=False): + def unpack_us_rc(self, pkt, check_parity=False): self.fmt_type = TLP_CPL self.lower_address = pkt.data[0] & 0xfff @@ -600,6 +546,8 @@ class TLP_us(TLP): self.tc = (pkt.data[2] >> 25) & 0x7 self.attr = (pkt.data[2] >> 28) & 0x7 + self.discontinue = pkt.discontinue + if self.length > 0: self.data = pkt.data[3:3+self.length] @@ -610,7 +558,7 @@ class TLP_us(TLP): if self.byte_count+(self.lower_address&3) > self.length*4: last_be = 0xf else: - last_be = 0xf >> ((self.byte_count+self.lower_address)&3) + last_be = 0xf >> ((4-self.byte_count-self.lower_address)&3) if len(self.data) == 1: first_be = first_be & last_be @@ -623,18 +571,12 @@ class TLP_us(TLP): if len(self.data) > 1: byte_en += [last_be] - # compute parity - parity = [dword_parity(d) ^ 0xf for d in pkt.data] + # check byte enables + assert byte_en == pkt.byte_en - # check sideband components - assert pkt.user[0] & (1 << 32) # is_sof_0 - - for k in range(0, len(pkt.data), int(dw/32)): - for l in range(int(dw/32)): - if k+l < len(byte_en): - assert (pkt.user[int(k/(dw/32))] >> l*4) & 0xf == byte_en[k+l] - if check_parity: - assert (pkt.user[int(k/(dw/32))] >> l*4+43) & 0xf == parity[k+l] + # check parity + if check_parity: + assert pkt.check_parity() return self @@ -692,6 +634,881 @@ class TLP_us(TLP): ) +class CQSource(object): + def __init__(self): + self.active = False + self.has_logic = False + self.queue = [] + + def send(self, frame): + self.queue.append(USPcieFrame(frame)) + + def count(self): + return len(self.queue) + + def empty(self): + return not self.queue + + def create_logic(self, + clk, + rst, + tdata=None, + tkeep=Signal(bool(True)), + tvalid=Signal(bool(False)), + tready=Signal(bool(True)), + tlast=Signal(bool(False)), + tuser=Signal(intbv(0)), + pause=0, + name=None + ): + + assert len(tdata) in [64, 128, 256] + assert len(tkeep)*32 == len(tdata) + assert len(tuser) in [85, 88] + + assert not self.has_logic + + self.has_logic = True + + @instance + def logic(): + frame = USPcieFrame() + data = [] + byte_en = [] + parity = [] + self.active = False + first = True + + while True: + yield clk.posedge, rst.posedge + + if rst: + data = [] + byte_en = [] + parity = [] + self.active = False + tdata.next = 0 + tkeep.next = 0 + tuser.next = 0 + tvalid.next = False + tlast.next = False + first = True + else: + tvalid.next = self.active and (tvalid or not pause) + if tready and tvalid: + tvalid.next = False + self.active = False + if not data and self.queue: + frame = self.queue.pop(0) + data = list(frame.data) + byte_en = list(frame.byte_en) + parity = list(frame.parity) + if name is not None: + print("[%s] Sending frame %s" % (name, repr(frame))) + first = True + if data and not self.active: + d = 0 + k = 0 + u = 0 + + if first: + u |= (frame.first_be & 0xf) + u |= (frame.last_be & 0xf) << 4 + u |= 1 << 40 # sop + + if frame.discontinue: + u |= 1 << 41 # discontinue + + for i in range(len(tkeep)): + if data: + d |= data.pop(0) << i*32 + k |= 1 << i + u |= byte_en.pop(0) << i*4+8 + u |= parity.pop(0) << i*4+53 + else: + u |= 0xf << i*4+53 + + tdata.next = d + tkeep.next = k + tuser.next = u + tvalid.next = not pause + tlast.next = len(data) == 0 + self.active = True + first = False + + return instances() + + +class CQSink(object): + def __init__(self): + self.has_logic = False + self.queue = [] + self.read_queue = [] + self.sync = Signal(intbv(0)) + + def recv(self): + if self.queue: + return self.queue.pop(0) + return None + + def count(self): + return len(self.queue) + + def empty(self): + return not self.queue + + def wait(self, timeout=0): + if self.queue: + return + if timeout: + yield self.sync, delay(timeout) + else: + yield self.sync + + def create_logic(self, + clk, + rst, + tdata=None, + tkeep=Signal(bool(True)), + tvalid=Signal(bool(False)), + tready=Signal(bool(True)), + tlast=Signal(bool(True)), + tuser=Signal(intbv(0)), + pause=0, + name=None + ): + + assert len(tdata) in [64, 128, 256] + assert len(tkeep)*32 == len(tdata) + assert len(tuser) in [85, 88] + + assert not self.has_logic + + self.has_logic = True + + tready_int = Signal(bool(False)) + tvalid_int = Signal(bool(False)) + + @always_comb + def pause_logic(): + tready.next = tready_int and not pause + tvalid_int.next = tvalid and not pause + + @instance + def logic(): + frame = USPcieFrame() + first = True + + while True: + yield clk.posedge, rst.posedge + + if rst: + tready_int.next = False + frame = USPcieFrame() + first = True + else: + tready_int.next = True + + if tvalid_int: + # zero tkeep not allowed + assert int(tkeep) != 0 + # tkeep must be contiguous + # i.e. 0b00011110 allowed, but 0b00011010 not allowed + b = int(tkeep) + while b & 1 == 0: + b = b >> 1 + while b & 1 == 1: + b = b >> 1 + assert b == 0 + # tkeep must not have gaps across cycles + if not first: + # not first cycle; lowest bit must be set + assert int(tkeep) & 1 + if not tlast: + # not last cycle; highest bit must be set + assert int(tkeep) & (1 << len(tkeep)-1) + + d = int(tdata) + u = int(tuser) + + if first: + frame.first_be = u & 0xf + frame.last_be = (u >> 4) & 0xf + assert tuser & (1 << 40) # sop + + if tuser & (1 << 41): + frame.discontinue = True + + for i in range(len(tkeep)): + if tkeep & (1 << i): + frame.data.append((d >> (i*32)) & 0xffffffff) + frame.byte_en.append((u >> (i*4+8)) & 0xf) + frame.parity.append((u >> (i*4+53)) & 0xf) + + first = False + if tlast: + self.queue.append(frame) + self.sync.next = not self.sync + if name is not None: + print("[%s] Got frame %s" % (name, repr(frame))) + frame = USPcieFrame() + first = True + + return instances() + + +class CCSource(object): + def __init__(self): + self.active = False + self.has_logic = False + self.queue = [] + + def send(self, frame): + self.queue.append(USPcieFrame(frame)) + + def count(self): + return len(self.queue) + + def empty(self): + return not self.queue + + def create_logic(self, + clk, + rst, + tdata=None, + tkeep=Signal(bool(True)), + tvalid=Signal(bool(False)), + tready=Signal(bool(True)), + tlast=Signal(bool(False)), + tuser=Signal(intbv(0)), + pause=0, + name=None + ): + + assert len(tdata) in [64, 128, 256] + assert len(tkeep)*32 == len(tdata) + assert len(tuser) == 33 + + assert not self.has_logic + + self.has_logic = True + + @instance + def logic(): + frame = USPcieFrame() + data = [] + parity = [] + self.active = False + first = True + + while True: + yield clk.posedge, rst.posedge + + if rst: + data = [] + parity = [] + self.active = False + tdata.next = 0 + tkeep.next = 0 + tuser.next = 0 + tvalid.next = False + tlast.next = False + first = True + else: + tvalid.next = self.active and (tvalid or not pause) + if tready and tvalid: + tvalid.next = False + self.active = False + if not data and self.queue: + frame = self.queue.pop(0) + data = list(frame.data) + parity = list(frame.parity) + if name is not None: + print("[%s] Sending frame %s" % (name, repr(frame))) + first = True + if data and not self.active: + d = 0 + k = 0 + u = 0 + + if frame.discontinue: + u |= 1 # discontinue + + for i in range(len(tkeep)): + if data: + d |= data.pop(0) << i*32 + k |= 1 << i + u |= parity.pop(0) << i*4+1 + else: + u |= 0xf << i*4+1 + + tdata.next = d + tkeep.next = k + tuser.next = u + tvalid.next = not pause + tlast.next = len(data) == 0 + self.active = True + first = False + + return instances() + + +class CCSink(object): + def __init__(self): + self.has_logic = False + self.queue = [] + self.read_queue = [] + self.sync = Signal(intbv(0)) + + def recv(self): + if self.queue: + return self.queue.pop(0) + return None + + def count(self): + return len(self.queue) + + def empty(self): + return not self.queue + + def wait(self, timeout=0): + if self.queue: + return + if timeout: + yield self.sync, delay(timeout) + else: + yield self.sync + + def create_logic(self, + clk, + rst, + tdata=None, + tkeep=Signal(bool(True)), + tvalid=Signal(bool(False)), + tready=Signal(bool(True)), + tlast=Signal(bool(True)), + tuser=Signal(intbv(0)), + pause=0, + name=None + ): + + assert len(tdata) in [64, 128, 256] + assert len(tkeep)*32 == len(tdata) + assert len(tuser) == 33 + + assert not self.has_logic + + self.has_logic = True + + tready_int = Signal(bool(False)) + tvalid_int = Signal(bool(False)) + + @always_comb + def pause_logic(): + tready.next = tready_int and not pause + tvalid_int.next = tvalid and not pause + + @instance + def logic(): + frame = USPcieFrame() + first = True + + while True: + yield clk.posedge, rst.posedge + + if rst: + tready_int.next = False + frame = USPcieFrame() + first = True + else: + tready_int.next = True + + if tvalid_int: + # zero tkeep not allowed + assert int(tkeep) != 0 + # tkeep must be contiguous + # i.e. 0b00011110 allowed, but 0b00011010 not allowed + b = int(tkeep) + while b & 1 == 0: + b = b >> 1 + while b & 1 == 1: + b = b >> 1 + assert b == 0 + # tkeep must not have gaps across cycles + if not first: + # not first cycle; lowest bit must be set + assert int(tkeep) & 1 + if not tlast: + # not last cycle; highest bit must be set + assert int(tkeep) & (1 << len(tkeep)-1) + + d = int(tdata) + u = int(tuser) + + if u & 1: + frame.discontinue = True + + for i in range(len(tkeep)): + if tkeep & (1 << i): + frame.data.append((d >> (i*32)) & 0xffffffff) + frame.parity.append((u >> (i*4+1)) & 0xf) + + first = False + if tlast: + self.queue.append(frame) + self.sync.next = not self.sync + if name is not None: + print("[%s] Got frame %s" % (name, repr(frame))) + frame = USPcieFrame() + first = True + + return instances() + + +class RQSource(object): + def __init__(self): + self.active = False + self.has_logic = False + self.queue = [] + + def send(self, frame): + self.queue.append(USPcieFrame(frame)) + + def count(self): + return len(self.queue) + + def empty(self): + return not self.queue + + def create_logic(self, + clk, + rst, + tdata=None, + tkeep=Signal(bool(True)), + tvalid=Signal(bool(False)), + tready=Signal(bool(True)), + tlast=Signal(bool(False)), + tuser=Signal(intbv(0)), + pause=0, + name=None + ): + + assert len(tdata) in [64, 128, 256] + assert len(tkeep)*32 == len(tdata) + assert len(tuser) in [60, 62] + + assert not self.has_logic + + self.has_logic = True + + @instance + def logic(): + frame = USPcieFrame() + data = [] + parity = [] + self.active = False + first = True + + while True: + yield clk.posedge, rst.posedge + + if rst: + data = [] + parity = [] + self.active = False + tdata.next = 0 + tkeep.next = 0 + tuser.next = 0 + tvalid.next = False + tlast.next = False + first = True + else: + tvalid.next = self.active and (tvalid or not pause) + if tready and tvalid: + tvalid.next = False + self.active = False + if not data and self.queue: + frame = self.queue.pop(0) + data = list(frame.data) + parity = list(frame.parity) + if name is not None: + print("[%s] Sending frame %s" % (name, repr(frame))) + first = True + if data and not self.active: + d = 0 + k = 0 + u = 0 + + if first: + u |= (frame.first_be & 0xf) + u |= (frame.last_be & 0xf) << 4 + + if frame.discontinue: + u |= 11 # discontinue + + for i in range(len(tkeep)): + if data: + d |= data.pop(0) << i*32 + k |= 1 << i + u |= parity.pop(0) << i*4+28 + else: + u |= 0xf << i*4+28 + + # TODO seq_num + # TODO tph + + tdata.next = d + tkeep.next = k + tuser.next = u + tvalid.next = not pause + tlast.next = len(data) == 0 + self.active = True + first = False + + return instances() + + +class RQSink(object): + def __init__(self): + self.has_logic = False + self.queue = [] + self.read_queue = [] + self.sync = Signal(intbv(0)) + + def recv(self): + if self.queue: + return self.queue.pop(0) + return None + + def count(self): + return len(self.queue) + + def empty(self): + return not self.queue + + def wait(self, timeout=0): + if self.queue: + return + if timeout: + yield self.sync, delay(timeout) + else: + yield self.sync + + def create_logic(self, + clk, + rst, + tdata=None, + tkeep=Signal(bool(True)), + tvalid=Signal(bool(False)), + tready=Signal(bool(True)), + tlast=Signal(bool(True)), + tuser=Signal(intbv(0)), + pause=0, + name=None + ): + + assert len(tdata) in [64, 128, 256] + assert len(tkeep)*32 == len(tdata) + assert len(tuser) in [60, 62] + + assert not self.has_logic + + self.has_logic = True + + tready_int = Signal(bool(False)) + tvalid_int = Signal(bool(False)) + + @always_comb + def pause_logic(): + tready.next = tready_int and not pause + tvalid_int.next = tvalid and not pause + + @instance + def logic(): + frame = USPcieFrame() + first = True + + while True: + yield clk.posedge, rst.posedge + + if rst: + tready_int.next = False + frame = USPcieFrame() + first = True + else: + tready_int.next = True + + if tvalid_int: + # zero tkeep not allowed + assert int(tkeep) != 0 + # tkeep must be contiguous + # i.e. 0b00011110 allowed, but 0b00011010 not allowed + b = int(tkeep) + while b & 1 == 0: + b = b >> 1 + while b & 1 == 1: + b = b >> 1 + assert b == 0 + # tkeep must not have gaps across cycles + if not first: + # not first cycle; lowest bit must be set + assert int(tkeep) & 1 + if not tlast: + # not last cycle; highest bit must be set + assert int(tkeep) & (1 << len(tkeep)-1) + + d = int(tdata) + u = int(tuser) + + if first: + frame.first_be = u & 0xf + frame.last_be = (u >> 4) & 0xf + + if u & (1 << 11): + frame.discontinue = True + + for i in range(len(tkeep)): + if tkeep & (1 << i): + frame.data.append((d >> (i*32)) & 0xffffffff) + frame.parity.append((u >> (i*4+28)) & 0xf) + + first = False + if tlast: + self.queue.append(frame) + self.sync.next = not self.sync + if name is not None: + print("[%s] Got frame %s" % (name, repr(frame))) + frame = USPcieFrame() + first = True + + return instances() + + +class RCSource(object): + def __init__(self): + self.active = False + self.has_logic = False + self.queue = [] + + def send(self, frame): + self.queue.append(USPcieFrame(frame)) + + def count(self): + return len(self.queue) + + def empty(self): + return not self.queue + + def create_logic(self, + clk, + rst, + tdata=None, + tkeep=Signal(bool(True)), + tvalid=Signal(bool(False)), + tready=Signal(bool(True)), + tlast=Signal(bool(False)), + tuser=Signal(intbv(0)), + pause=0, + name=None + ): + + assert len(tdata) in [64, 128, 256] + assert len(tkeep)*32 == len(tdata) + assert len(tuser) == 75 + + assert not self.has_logic + + self.has_logic = True + + @instance + def logic(): + frame = USPcieFrame() + data = [] + byte_en = [] + parity = [] + self.active = False + first = True + + while True: + yield clk.posedge, rst.posedge + + if rst: + data = [] + byte_en = [] + parity = [] + self.active = False + tdata.next = 0 + tkeep.next = 0 + tuser.next = 0 + tvalid.next = False + tlast.next = False + first = True + else: + tvalid.next = self.active and (tvalid or not pause) + if tready and tvalid: + tvalid.next = False + self.active = False + if not data and self.queue: + frame = self.queue.pop(0) + data = list(frame.data) + byte_en = list(frame.byte_en) + parity = list(frame.parity) + if name is not None: + print("[%s] Sending frame %s" % (name, repr(frame))) + first = True + if data and not self.active: + d = 0 + k = 0 + u = 0 + + if first: + u |= 1 << 32 # is_sof_0 + + if frame.discontinue: + u |= 1 << 42 # discontinue + + last_lane = 0 + + for i in range(len(tkeep)): + if data: + d |= data.pop(0) << i*32 + k |= 1 << i + u |= byte_en.pop(0) << i*4 + u |= parity.pop(0) << i*4+43 + last_lane = i + else: + u |= 0xf << i*4+43 + + if not data: + u |= (1 | last_lane << 1) << 34 # is_eof_0 + + tdata.next = d + tkeep.next = k + tuser.next = u + tvalid.next = not pause + tlast.next = len(data) == 0 + self.active = True + first = False + + return instances() + + +class RCSink(object): + def __init__(self): + self.has_logic = False + self.queue = [] + self.read_queue = [] + self.sync = Signal(intbv(0)) + + def recv(self): + if self.queue: + return self.queue.pop(0) + return None + + def count(self): + return len(self.queue) + + def empty(self): + return not self.queue + + def wait(self, timeout=0): + if self.queue: + return + if timeout: + yield self.sync, delay(timeout) + else: + yield self.sync + + def create_logic(self, + clk, + rst, + tdata=None, + tkeep=Signal(bool(True)), + tvalid=Signal(bool(False)), + tready=Signal(bool(True)), + tlast=Signal(bool(True)), + tuser=Signal(intbv(0)), + pause=0, + name=None + ): + + assert len(tdata) in [64, 128, 256] + assert len(tkeep)*32 == len(tdata) + assert len(tuser) == 75 + + assert not self.has_logic + + self.has_logic = True + + tready_int = Signal(bool(False)) + tvalid_int = Signal(bool(False)) + + @always_comb + def pause_logic(): + tready.next = tready_int and not pause + tvalid_int.next = tvalid and not pause + + @instance + def logic(): + frame = USPcieFrame() + first = True + + while True: + yield clk.posedge, rst.posedge + + if rst: + tready_int.next = False + frame = USPcieFrame() + first = True + else: + tready_int.next = True + + if tvalid_int: + # zero tkeep not allowed + assert int(tkeep) != 0 + # tkeep must be contiguous + # i.e. 0b00011110 allowed, but 0b00011010 not allowed + b = int(tkeep) + while b & 1 == 0: + b = b >> 1 + while b & 1 == 1: + b = b >> 1 + assert b == 0 + # tkeep must not have gaps across cycles + if not first: + # not first cycle; lowest bit must be set + assert int(tkeep) & 1 + if not tlast: + # not last cycle; highest bit must be set + assert int(tkeep) & (1 << len(tkeep)-1) + + d = int(tdata) + u = int(tuser) + + if first: + assert tuser & (1 << 32) # is_sof_0 + + if u & (1 << 42): + frame.discontinue = True + + for i in range(len(tkeep)): + if tkeep & (1 << i): + frame.data.append((d >> (i*32)) & 0xffffffff) + frame.byte_en.append((u >> (i*4)) & 0xf) + frame.parity.append((u >> (i*4+43)) & 0xf) + + first = False + if tlast: + self.queue.append(frame) + self.sync.next = not self.sync + if name is not None: + print("[%s] Got frame %s" % (name, repr(frame))) + frame = USPcieFrame() + first = True + + return instances() + + class UltrascalePCIeFunction(Endpoint, MSICapability, MSIXCapability): def __init__(self): super(UltrascalePCIeFunction, self).__init__() @@ -740,10 +1557,10 @@ class UltrascalePCIe(Device): self.config_space_enable = False - self.cq_source = axis_ep.AXIStreamSource() - self.cc_sink = axis_ep.AXIStreamSink() - self.rq_sink = axis_ep.AXIStreamSink() - self.rc_source = axis_ep.AXIStreamSource() + self.cq_source = CQSource() + self.cc_sink = CCSink() + self.rq_sink = RQSink() + self.rc_source = RCSource() self.make_function() @@ -1403,7 +2220,7 @@ class UltrascalePCIe(Device): while self.cq_np_queue and self.cq_np_req_count > 0: tlp = self.cq_np_queue.pop(0) self.cq_np_req_count -= 1 - self.cq_source.send(tlp.pack_us_cq(self.dw)) + self.cq_source.send(tlp.pack_us_cq()) # handle new requests while self.cq_queue: @@ -1415,13 +2232,13 @@ class UltrascalePCIe(Device): if self.cq_np_req_count > 0: # have credit, can forward self.cq_np_req_count -= 1 - self.cq_source.send(tlp.pack_us_cq(self.dw)) + self.cq_source.send(tlp.pack_us_cq()) else: # no credits, put it in the queue self.cq_np_queue.append(tlp) else: # posted request - self.cq_source.send(tlp.pack_us_cq(self.dw)) + self.cq_source.send(tlp.pack_us_cq()) pcie_cq_np_req_count.next = self.cq_np_req_count @@ -1429,7 +2246,7 @@ class UltrascalePCIe(Device): while not self.cc_sink.empty(): pkt = self.cc_sink.recv() - tlp = TLP_us().unpack_us_cc(pkt, self.dw, self.enable_parity) + tlp = TLP_us().unpack_us_cc(pkt, self.enable_parity) if not tlp.completer_id_enable: tlp.completer_id = PcieId(self.bus_num, self.device_num, tlp.completer_id.function) @@ -1441,7 +2258,7 @@ class UltrascalePCIe(Device): while not self.rq_sink.empty(): pkt = self.rq_sink.recv() - tlp = TLP_us().unpack_us_rq(pkt, self.dw, self.enable_parity) + tlp = TLP_us().unpack_us_rq(pkt, self.enable_parity) if not tlp.requester_id_enable: tlp.requester_id = PcieId(self.bus_num, self.device_num, tlp.requester_id.function) @@ -1460,7 +2277,7 @@ class UltrascalePCIe(Device): # handle requester completions while self.rc_queue: tlp = self.rc_queue.pop(0) - self.rc_source.send(tlp.pack_us_rc(self.dw)) + self.rc_source.send(tlp.pack_us_rc()) # transmit flow control #pcie_tfc_nph_av diff --git a/tb/pcie_usp.py b/tb/pcie_usp.py index 36f64b1..1739cd7 100644 --- a/tb/pcie_usp.py +++ b/tb/pcie_usp.py @@ -80,10 +80,10 @@ class UltrascalePlusPCIe(Device): self.config_space_enable = False - self.cq_source = axis_ep.AXIStreamSource() - self.cc_sink = axis_ep.AXIStreamSink() - self.rq_sink = axis_ep.AXIStreamSink() - self.rc_source = axis_ep.AXIStreamSource() + self.cq_source = CQSource() + self.cc_sink = CCSink() + self.rq_sink = RQSink() + self.rc_source = RCSource() self.make_function() @@ -748,7 +748,7 @@ class UltrascalePlusPCIe(Device): while self.cq_np_queue and self.cq_np_req_count > 0: tlp = self.cq_np_queue.pop(0) self.cq_np_req_count -= 1 - self.cq_source.send(tlp.pack_us_cq(self.dw)) + self.cq_source.send(tlp.pack_us_cq()) # handle new requests while self.cq_queue: @@ -760,13 +760,13 @@ class UltrascalePlusPCIe(Device): if self.cq_np_req_count > 0: # have credit, can forward self.cq_np_req_count -= 1 - self.cq_source.send(tlp.pack_us_cq(self.dw)) + self.cq_source.send(tlp.pack_us_cq()) else: # no credits, put it in the queue self.cq_np_queue.append(tlp) else: # posted request - self.cq_source.send(tlp.pack_us_cq(self.dw)) + self.cq_source.send(tlp.pack_us_cq()) pcie_cq_np_req_count.next = self.cq_np_req_count @@ -774,7 +774,7 @@ class UltrascalePlusPCIe(Device): while not self.cc_sink.empty(): pkt = self.cc_sink.recv() - tlp = TLP_us().unpack_us_cc(pkt, self.dw, self.enable_parity) + tlp = TLP_us().unpack_us_cc(pkt, self.enable_parity) if not tlp.completer_id_enable: tlp.completer_id = PcieId(self.bus_num, self.device_num, tlp.completer_id.function) @@ -786,7 +786,7 @@ class UltrascalePlusPCIe(Device): while not self.rq_sink.empty(): pkt = self.rq_sink.recv() - tlp = TLP_us().unpack_us_rq(pkt, self.dw, self.enable_parity) + tlp = TLP_us().unpack_us_rq(pkt, self.enable_parity) if not tlp.requester_id_enable: tlp.requester_id = PcieId(self.bus_num, self.device_num, tlp.requester_id.function) @@ -805,7 +805,7 @@ class UltrascalePlusPCIe(Device): # handle requester completions while self.rc_queue: tlp = self.rc_queue.pop(0) - self.rc_source.send(tlp.pack_us_rc(self.dw)) + self.rc_source.send(tlp.pack_us_rc()) # transmit flow control #pcie_tfc_nph_av diff --git a/tb/test_pcie_us.py b/tb/test_pcie_us.py index 20291ce..ecc614f 100755 --- a/tb/test_pcie_us.py +++ b/tb/test_pcie_us.py @@ -27,7 +27,6 @@ from myhdl import * import struct import os -import axis_ep import pcie import pcie_us @@ -223,7 +222,7 @@ def bench(): pcie_perstn1_out=Signal(bool(0)) # sources and sinks - cq_sink = axis_ep.AXIStreamSink() + cq_sink = pcie_us.CQSink() cq_sink_logic = cq_sink.create_logic( user_clk, @@ -237,7 +236,7 @@ def bench(): name='cq_sink' ) - cc_source = axis_ep.AXIStreamSource() + cc_source = pcie_us.CCSource() cc_source_logic = cc_source.create_logic( user_clk, @@ -251,7 +250,7 @@ def bench(): name='cc_source' ) - rq_source = axis_ep.AXIStreamSource() + rq_source = pcie_us.RQSource() rq_source_logic = rq_source.create_logic( user_clk, @@ -265,7 +264,7 @@ def bench(): name='rq_source' ) - rc_sink = axis_ep.AXIStreamSink() + rc_sink = pcie_us.RCSink() rc_sink_logic = rc_sink.create_logic( user_clk, @@ -501,7 +500,7 @@ def bench(): if not cq_sink.empty(): pkt = cq_sink.recv() - tlp = pcie_us.TLP_us().unpack_us_cq(pkt, dw) + tlp = pcie_us.TLP_us().unpack_us_cq(pkt) print(tlp) @@ -539,7 +538,7 @@ def bench(): cpl.byte_count = 4 cpl.length = 1 - cc_source.send(cpl.pack_us_cc(dw)) + cc_source.send(cpl.pack_us_cc()) elif (tlp.fmt_type == pcie.TLP_IO_WRITE): print("IO write") @@ -569,7 +568,7 @@ def bench(): if start_offset is not None and offset != start_offset: regions[region][addr+start_offset:addr+offset] = data[start_offset:offset] - cc_source.send(cpl.pack_us_cc(dw)) + cc_source.send(cpl.pack_us_cc()) if (tlp.fmt_type == pcie.TLP_MEM_READ or tlp.fmt_type == pcie.TLP_MEM_READ_64): print("Memory read") @@ -604,7 +603,7 @@ def bench(): cpl.set_data(data[offset+n:offset+n+byte_length]) print("Completion: %s" % (repr(cpl))) - cc_source.send(cpl.pack_us_cc(dw)) + cc_source.send(cpl.pack_us_cc()) n += byte_length addr += byte_length @@ -745,14 +744,14 @@ def bench(): current_tag = (current_tag % 31) + 1 - rq_source.send(tlp.pack_us_rq(dw)) + rq_source.send(tlp.pack_us_rq()) yield rc_sink.wait(100) pkt = rc_sink.recv() if not pkt: raise Exception("Timeout") - cpl = pcie_us.TLP_us().unpack_us_rc(pkt, dw) + cpl = pcie_us.TLP_us().unpack_us_rc(pkt) if cpl.status != pcie.CPL_STATUS_SC: raise Exception("Unsuccessful completion") @@ -783,14 +782,14 @@ def bench(): current_tag = (current_tag % 31) + 1 - rq_source.send(tlp.pack_us_rq(dw)) + rq_source.send(tlp.pack_us_rq()) yield rc_sink.wait(100) pkt = rc_sink.recv() if not pkt: raise Exception("Timeout") - cpl = pcie_us.TLP_us().unpack_us_rc(pkt, dw) + cpl = pcie_us.TLP_us().unpack_us_rc(pkt) if cpl.status != pcie.CPL_STATUS_SC: raise Exception("Unsuccessful completion") @@ -831,7 +830,7 @@ def bench(): current_tag = (current_tag % 31) + 1 - rq_source.send(tlp.pack_us_rq(dw)) + rq_source.send(tlp.pack_us_rq()) n += byte_length addr += byte_length @@ -865,7 +864,7 @@ def bench(): current_tag = (current_tag % 31) + 1 - rq_source.send(tlp.pack_us_rq(dw)) + rq_source.send(tlp.pack_us_rq()) m = 0 @@ -876,7 +875,7 @@ def bench(): if not pkt: raise Exception("Timeout") - cpl = pcie_us.TLP_us().unpack_us_rc(pkt, dw) + cpl = pcie_us.TLP_us().unpack_us_rc(pkt) if cpl.status != pcie.CPL_STATUS_SC: raise Exception("Unsuccessful completion") diff --git a/tb/test_pcie_us_axil_master_128.py b/tb/test_pcie_us_axil_master_128.py index 0f172a2..47132bb 100755 --- a/tb/test_pcie_us_axil_master_128.py +++ b/tb/test_pcie_us_axil_master_128.py @@ -26,7 +26,6 @@ THE SOFTWARE. from myhdl import * import os -import axis_ep import axil import pcie_us @@ -98,7 +97,7 @@ def bench(): status_error_uncor = Signal(bool(0)) # sources and sinks - cq_source = axis_ep.AXIStreamSource() + cq_source = pcie_us.CQSource() cq_source_logic = cq_source.create_logic( clk, @@ -112,7 +111,7 @@ def bench(): name='cq_source' ) - cc_sink = axis_ep.AXIStreamSink() + cc_sink = pcie_us.CCSink() cc_sink_logic = cc_sink.create_logic( clk, @@ -258,7 +257,7 @@ def bench(): tlp.set_be_data(0x0000, b'\x11\x22\x33\x44') tlp.address = 0x0000 - cq_source.send(tlp.pack_us_cq(AXIS_PCIE_DATA_WIDTH)) + cq_source.send(tlp.pack_us_cq()) yield delay(100) @@ -287,12 +286,12 @@ def bench(): tlp.set_be_data(0x0000, b'\x11\x22\x33\x44') tlp.address = 0x0000 - cq_source.send(tlp.pack_us_cq(AXIS_PCIE_DATA_WIDTH)) + cq_source.send(tlp.pack_us_cq()) yield cc_sink.wait(500) pkt = cc_sink.recv() - rx_tlp = pcie_us.TLP_us().unpack_us_cc(pkt, AXIS_PCIE_DATA_WIDTH) + rx_tlp = pcie_us.TLP_us().unpack_us_cc(pkt) print(rx_tlp) @@ -326,12 +325,12 @@ def bench(): tlp.set_be(0x0000, 4) tlp.address = 0x0000 - cq_source.send(tlp.pack_us_cq(AXIS_PCIE_DATA_WIDTH)) + cq_source.send(tlp.pack_us_cq()) yield cc_sink.wait(500) pkt = cc_sink.recv() - rx_tlp = pcie_us.TLP_us().unpack_us_cc(pkt, AXIS_PCIE_DATA_WIDTH) + rx_tlp = pcie_us.TLP_us().unpack_us_cc(pkt) print(rx_tlp) @@ -364,12 +363,12 @@ def bench(): tlp.set_be(0x0000, 4) tlp.address = 0x0000 - cq_source.send(tlp.pack_us_cq(AXIS_PCIE_DATA_WIDTH)) + cq_source.send(tlp.pack_us_cq()) yield cc_sink.wait(500) pkt = cc_sink.recv() - rx_tlp = pcie_us.TLP_us().unpack_us_cc(pkt, AXIS_PCIE_DATA_WIDTH) + rx_tlp = pcie_us.TLP_us().unpack_us_cc(pkt) print(rx_tlp) @@ -405,7 +404,7 @@ def bench(): tlp.set_be_data(256*(16*offset+length)+offset, b'\x11\x22\x33\x44'[0:length]) tlp.address = 256*(16*offset+length)+offset - cq_source.send(tlp.pack_us_cq(AXIS_PCIE_DATA_WIDTH)) + cq_source.send(tlp.pack_us_cq()) yield delay(100) @@ -439,12 +438,12 @@ def bench(): tlp.set_be(256*(16*offset+length)+offset, length) tlp.address = 256*(16*offset+length)+offset - cq_source.send(tlp.pack_us_cq(AXIS_PCIE_DATA_WIDTH)) + cq_source.send(tlp.pack_us_cq()) yield cc_sink.wait(500) pkt = cc_sink.recv() - rx_tlp = pcie_us.TLP_us().unpack_us_cc(pkt, AXIS_PCIE_DATA_WIDTH) + rx_tlp = pcie_us.TLP_us().unpack_us_cc(pkt) print(rx_tlp) @@ -476,7 +475,7 @@ def bench(): tlp.set_be_data(0x0000, bytearray(range(64))) tlp.address = 0x0000 - cq_source.send(tlp.pack_us_cq(AXIS_PCIE_DATA_WIDTH)) + cq_source.send(tlp.pack_us_cq()) yield delay(100) @@ -501,12 +500,12 @@ def bench(): tlp.set_be(0x0000, 64) tlp.address = 0x0000 - cq_source.send(tlp.pack_us_cq(AXIS_PCIE_DATA_WIDTH)) + cq_source.send(tlp.pack_us_cq()) yield cc_sink.wait(500) pkt = cc_sink.recv() - rx_tlp = pcie_us.TLP_us().unpack_us_cc(pkt, AXIS_PCIE_DATA_WIDTH) + rx_tlp = pcie_us.TLP_us().unpack_us_cc(pkt) print(rx_tlp) diff --git a/tb/test_pcie_us_axil_master_256.py b/tb/test_pcie_us_axil_master_256.py index 50ad4bd..0d436b8 100755 --- a/tb/test_pcie_us_axil_master_256.py +++ b/tb/test_pcie_us_axil_master_256.py @@ -26,7 +26,6 @@ THE SOFTWARE. from myhdl import * import os -import axis_ep import axil import pcie_us @@ -98,7 +97,7 @@ def bench(): status_error_uncor = Signal(bool(0)) # sources and sinks - cq_source = axis_ep.AXIStreamSource() + cq_source = pcie_us.CQSource() cq_source_logic = cq_source.create_logic( clk, @@ -112,7 +111,7 @@ def bench(): name='cq_source' ) - cc_sink = axis_ep.AXIStreamSink() + cc_sink = pcie_us.CCSink() cc_sink_logic = cc_sink.create_logic( clk, @@ -258,7 +257,7 @@ def bench(): tlp.set_be_data(0x0000, b'\x11\x22\x33\x44') tlp.address = 0x0000 - cq_source.send(tlp.pack_us_cq(AXIS_PCIE_DATA_WIDTH)) + cq_source.send(tlp.pack_us_cq()) yield delay(100) @@ -287,12 +286,12 @@ def bench(): tlp.set_be_data(0x0000, b'\x11\x22\x33\x44') tlp.address = 0x0000 - cq_source.send(tlp.pack_us_cq(AXIS_PCIE_DATA_WIDTH)) + cq_source.send(tlp.pack_us_cq()) yield cc_sink.wait(500) pkt = cc_sink.recv() - rx_tlp = pcie_us.TLP_us().unpack_us_cc(pkt, AXIS_PCIE_DATA_WIDTH) + rx_tlp = pcie_us.TLP_us().unpack_us_cc(pkt) print(rx_tlp) @@ -326,12 +325,12 @@ def bench(): tlp.set_be(0x0000, 4) tlp.address = 0x0000 - cq_source.send(tlp.pack_us_cq(AXIS_PCIE_DATA_WIDTH)) + cq_source.send(tlp.pack_us_cq()) yield cc_sink.wait(500) pkt = cc_sink.recv() - rx_tlp = pcie_us.TLP_us().unpack_us_cc(pkt, AXIS_PCIE_DATA_WIDTH) + rx_tlp = pcie_us.TLP_us().unpack_us_cc(pkt) print(rx_tlp) @@ -364,12 +363,12 @@ def bench(): tlp.set_be(0x0000, 4) tlp.address = 0x0000 - cq_source.send(tlp.pack_us_cq(AXIS_PCIE_DATA_WIDTH)) + cq_source.send(tlp.pack_us_cq()) yield cc_sink.wait(500) pkt = cc_sink.recv() - rx_tlp = pcie_us.TLP_us().unpack_us_cc(pkt, AXIS_PCIE_DATA_WIDTH) + rx_tlp = pcie_us.TLP_us().unpack_us_cc(pkt) print(rx_tlp) @@ -405,7 +404,7 @@ def bench(): tlp.set_be_data(256*(16*offset+length)+offset, b'\x11\x22\x33\x44'[0:length]) tlp.address = 256*(16*offset+length)+offset - cq_source.send(tlp.pack_us_cq(AXIS_PCIE_DATA_WIDTH)) + cq_source.send(tlp.pack_us_cq()) yield delay(100) @@ -439,12 +438,12 @@ def bench(): tlp.set_be(256*(16*offset+length)+offset, length) tlp.address = 256*(16*offset+length)+offset - cq_source.send(tlp.pack_us_cq(AXIS_PCIE_DATA_WIDTH)) + cq_source.send(tlp.pack_us_cq()) yield cc_sink.wait(500) pkt = cc_sink.recv() - rx_tlp = pcie_us.TLP_us().unpack_us_cc(pkt, AXIS_PCIE_DATA_WIDTH) + rx_tlp = pcie_us.TLP_us().unpack_us_cc(pkt) print(rx_tlp) @@ -476,7 +475,7 @@ def bench(): tlp.set_be_data(0x0000, bytearray(range(64))) tlp.address = 0x0000 - cq_source.send(tlp.pack_us_cq(AXIS_PCIE_DATA_WIDTH)) + cq_source.send(tlp.pack_us_cq()) yield delay(100) @@ -501,12 +500,12 @@ def bench(): tlp.set_be(0x0000, 64) tlp.address = 0x0000 - cq_source.send(tlp.pack_us_cq(AXIS_PCIE_DATA_WIDTH)) + cq_source.send(tlp.pack_us_cq()) yield cc_sink.wait(500) pkt = cc_sink.recv() - rx_tlp = pcie_us.TLP_us().unpack_us_cc(pkt, AXIS_PCIE_DATA_WIDTH) + rx_tlp = pcie_us.TLP_us().unpack_us_cc(pkt) print(rx_tlp) diff --git a/tb/test_pcie_us_axil_master_64.py b/tb/test_pcie_us_axil_master_64.py index d91f159..e2cb932 100755 --- a/tb/test_pcie_us_axil_master_64.py +++ b/tb/test_pcie_us_axil_master_64.py @@ -26,7 +26,6 @@ THE SOFTWARE. from myhdl import * import os -import axis_ep import axil import pcie_us @@ -98,7 +97,7 @@ def bench(): status_error_uncor = Signal(bool(0)) # sources and sinks - cq_source = axis_ep.AXIStreamSource() + cq_source = pcie_us.CQSource() cq_source_logic = cq_source.create_logic( clk, @@ -112,7 +111,7 @@ def bench(): name='cq_source' ) - cc_sink = axis_ep.AXIStreamSink() + cc_sink = pcie_us.CCSink() cc_sink_logic = cc_sink.create_logic( clk, @@ -258,7 +257,7 @@ def bench(): tlp.set_be_data(0x0000, b'\x11\x22\x33\x44') tlp.address = 0x0000 - cq_source.send(tlp.pack_us_cq(AXIS_PCIE_DATA_WIDTH)) + cq_source.send(tlp.pack_us_cq()) yield delay(100) @@ -287,12 +286,12 @@ def bench(): tlp.set_be_data(0x0000, b'\x11\x22\x33\x44') tlp.address = 0x0000 - cq_source.send(tlp.pack_us_cq(AXIS_PCIE_DATA_WIDTH)) + cq_source.send(tlp.pack_us_cq()) yield cc_sink.wait(500) pkt = cc_sink.recv() - rx_tlp = pcie_us.TLP_us().unpack_us_cc(pkt, AXIS_PCIE_DATA_WIDTH) + rx_tlp = pcie_us.TLP_us().unpack_us_cc(pkt) print(rx_tlp) @@ -326,12 +325,12 @@ def bench(): tlp.set_be(0x0000, 4) tlp.address = 0x0000 - cq_source.send(tlp.pack_us_cq(AXIS_PCIE_DATA_WIDTH)) + cq_source.send(tlp.pack_us_cq()) yield cc_sink.wait(500) pkt = cc_sink.recv() - rx_tlp = pcie_us.TLP_us().unpack_us_cc(pkt, AXIS_PCIE_DATA_WIDTH) + rx_tlp = pcie_us.TLP_us().unpack_us_cc(pkt) print(rx_tlp) @@ -364,12 +363,12 @@ def bench(): tlp.set_be(0x0000, 4) tlp.address = 0x0000 - cq_source.send(tlp.pack_us_cq(AXIS_PCIE_DATA_WIDTH)) + cq_source.send(tlp.pack_us_cq()) yield cc_sink.wait(500) pkt = cc_sink.recv() - rx_tlp = pcie_us.TLP_us().unpack_us_cc(pkt, AXIS_PCIE_DATA_WIDTH) + rx_tlp = pcie_us.TLP_us().unpack_us_cc(pkt) print(rx_tlp) @@ -405,7 +404,7 @@ def bench(): tlp.set_be_data(256*(16*offset+length)+offset, b'\x11\x22\x33\x44'[0:length]) tlp.address = 256*(16*offset+length)+offset - cq_source.send(tlp.pack_us_cq(AXIS_PCIE_DATA_WIDTH)) + cq_source.send(tlp.pack_us_cq()) yield delay(100) @@ -439,12 +438,12 @@ def bench(): tlp.set_be(256*(16*offset+length)+offset, length) tlp.address = 256*(16*offset+length)+offset - cq_source.send(tlp.pack_us_cq(AXIS_PCIE_DATA_WIDTH)) + cq_source.send(tlp.pack_us_cq()) yield cc_sink.wait(500) pkt = cc_sink.recv() - rx_tlp = pcie_us.TLP_us().unpack_us_cc(pkt, AXIS_PCIE_DATA_WIDTH) + rx_tlp = pcie_us.TLP_us().unpack_us_cc(pkt) print(rx_tlp) @@ -476,7 +475,7 @@ def bench(): tlp.set_be_data(0x0000, bytearray(range(64))) tlp.address = 0x0000 - cq_source.send(tlp.pack_us_cq(AXIS_PCIE_DATA_WIDTH)) + cq_source.send(tlp.pack_us_cq()) yield delay(100) @@ -501,12 +500,12 @@ def bench(): tlp.set_be(0x0000, 64) tlp.address = 0x0000 - cq_source.send(tlp.pack_us_cq(AXIS_PCIE_DATA_WIDTH)) + cq_source.send(tlp.pack_us_cq()) yield cc_sink.wait(500) pkt = cc_sink.recv() - rx_tlp = pcie_us.TLP_us().unpack_us_cc(pkt, AXIS_PCIE_DATA_WIDTH) + rx_tlp = pcie_us.TLP_us().unpack_us_cc(pkt) print(rx_tlp) diff --git a/tb/test_pcie_usp.py b/tb/test_pcie_usp.py index bf24c6e..e71923c 100755 --- a/tb/test_pcie_usp.py +++ b/tb/test_pcie_usp.py @@ -27,7 +27,6 @@ from myhdl import * import struct import os -import axis_ep import pcie import pcie_usp @@ -221,7 +220,7 @@ def bench(): phy_rdy_out=Signal(bool(0)) # sources and sinks - cq_sink = axis_ep.AXIStreamSink() + cq_sink = pcie_usp.CQSink() cq_sink_logic = cq_sink.create_logic( user_clk, @@ -235,7 +234,7 @@ def bench(): name='cq_sink' ) - cc_source = axis_ep.AXIStreamSource() + cc_source = pcie_usp.CCSource() cc_source_logic = cc_source.create_logic( user_clk, @@ -249,7 +248,7 @@ def bench(): name='cc_source' ) - rq_source = axis_ep.AXIStreamSource() + rq_source = pcie_usp.RQSource() rq_source_logic = rq_source.create_logic( user_clk, @@ -263,7 +262,7 @@ def bench(): name='rq_source' ) - rc_sink = axis_ep.AXIStreamSink() + rc_sink = pcie_usp.RCSink() rc_sink_logic = rc_sink.create_logic( user_clk, @@ -497,7 +496,7 @@ def bench(): if not cq_sink.empty(): pkt = cq_sink.recv() - tlp = pcie_usp.TLP_us().unpack_us_cq(pkt, dw) + tlp = pcie_usp.TLP_us().unpack_us_cq(pkt) print(tlp) @@ -535,7 +534,7 @@ def bench(): cpl.byte_count = 4 cpl.length = 1 - cc_source.send(cpl.pack_us_cc(dw)) + cc_source.send(cpl.pack_us_cc()) elif (tlp.fmt_type == pcie.TLP_IO_WRITE): print("IO write") @@ -565,7 +564,7 @@ def bench(): if start_offset is not None and offset != start_offset: regions[region][addr+start_offset:addr+offset] = data[start_offset:offset] - cc_source.send(cpl.pack_us_cc(dw)) + cc_source.send(cpl.pack_us_cc()) if (tlp.fmt_type == pcie.TLP_MEM_READ or tlp.fmt_type == pcie.TLP_MEM_READ_64): print("Memory read") @@ -600,7 +599,7 @@ def bench(): cpl.set_data(data[offset+n:offset+n+byte_length]) print("Completion: %s" % (repr(cpl))) - cc_source.send(cpl.pack_us_cc(dw)) + cc_source.send(cpl.pack_us_cc()) n += byte_length addr += byte_length @@ -741,14 +740,14 @@ def bench(): current_tag = (current_tag % 31) + 1 - rq_source.send(tlp.pack_us_rq(dw)) + rq_source.send(tlp.pack_us_rq()) yield rc_sink.wait(100) pkt = rc_sink.recv() if not pkt: raise Exception("Timeout") - cpl = pcie_usp.TLP_us().unpack_us_rc(pkt, dw) + cpl = pcie_usp.TLP_us().unpack_us_rc(pkt) if cpl.status != pcie.CPL_STATUS_SC: raise Exception("Unsuccessful completion") @@ -779,14 +778,14 @@ def bench(): current_tag = (current_tag % 31) + 1 - rq_source.send(tlp.pack_us_rq(dw)) + rq_source.send(tlp.pack_us_rq()) yield rc_sink.wait(100) pkt = rc_sink.recv() if not pkt: raise Exception("Timeout") - cpl = pcie_usp.TLP_us().unpack_us_rc(pkt, dw) + cpl = pcie_usp.TLP_us().unpack_us_rc(pkt) if cpl.status != pcie.CPL_STATUS_SC: raise Exception("Unsuccessful completion") @@ -827,7 +826,7 @@ def bench(): current_tag = (current_tag % 31) + 1 - rq_source.send(tlp.pack_us_rq(dw)) + rq_source.send(tlp.pack_us_rq()) n += byte_length addr += byte_length @@ -861,7 +860,7 @@ def bench(): current_tag = (current_tag % 31) + 1 - rq_source.send(tlp.pack_us_rq(dw)) + rq_source.send(tlp.pack_us_rq()) m = 0 @@ -872,7 +871,7 @@ def bench(): if not pkt: raise Exception("Timeout") - cpl = pcie_usp.TLP_us().unpack_us_rc(pkt, dw) + cpl = pcie_usp.TLP_us().unpack_us_rc(pkt) if cpl.status != pcie.CPL_STATUS_SC: raise Exception("Unsuccessful completion")