Add ExaNIC X10 example design
This commit is contained in:
Alex Forencich
parent
8ecf4a22ef
commit
9c176b0916
25
example/ExaNIC_X10/fpga/Makefile
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25
example/ExaNIC_X10/fpga/Makefile
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# Targets
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TARGETS:=
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# Subdirectories
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SUBDIRS = fpga
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SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS))
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# Rules
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.PHONY: all
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all: $(SUBDIRS) $(TARGETS)
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.PHONY: $(SUBDIRS)
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$(SUBDIRS):
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cd $@ && $(MAKE)
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.PHONY: $(SUBDIRS_CLEAN)
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$(SUBDIRS_CLEAN):
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cd $(@:.clean=) && $(MAKE) clean
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.PHONY: clean
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clean: $(SUBDIRS_CLEAN)
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-rm -rf $(TARGETS)
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program:
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#djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit
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26
example/ExaNIC_X10/fpga/README.md
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26
example/ExaNIC_X10/fpga/README.md
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# Verilog Ethernet ExaNIC X10 Example Design
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## Introduction
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This example design targets the Exablaze ExaNIC X10 FPGA board.
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The design implements the PCIe AXI lite master module, the PCIe AXI master
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module, and the PCIe AXI DMA module. A very simple Linux driver is included
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to test the FPGA design.
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FPGA: xcku035-fbva676-2-c
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## How to build
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Run make to build. Ensure that the Xilinx Vivado toolchain components are
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in PATH.
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Run make to build the driver. Ensure the headers for the running kernel are
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installed, otherwise the driver cannot be compiled.
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## How to test
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Run make program to program the ExaNIC X10 board with Vivado. Then load the
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driver with insmod example.ko. Check dmesg for the output.
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118
example/ExaNIC_X10/fpga/common/vivado.mk
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118
example/ExaNIC_X10/fpga/common/vivado.mk
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###################################################################
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#
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# Xilinx Vivado FPGA Makefile
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#
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# Copyright (c) 2016 Alex Forencich
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#
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###################################################################
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#
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# Parameters:
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# FPGA_TOP - Top module name
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# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale)
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# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e)
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# SYN_FILES - space-separated list of source files
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# INC_FILES - space-separated list of include files
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# XDC_FILES - space-separated list of timing constraint files
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# XCI_FILES - space-separated list of IP XCI files
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#
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# Example:
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#
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# FPGA_TOP = fpga
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# FPGA_FAMILY = VirtexUltrascale
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# FPGA_DEVICE = xcvu095-ffva2104-2-e
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# SYN_FILES = rtl/fpga.v
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# XDC_FILES = fpga.xdc
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# XCI_FILES = ip/pcspma.xci
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# include ../common/vivado.mk
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#
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###################################################################
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# phony targets
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.PHONY: clean fpga
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# prevent make from deleting intermediate files and reports
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.PRECIOUS: %.xpr %.bit %.mcs %.prm
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.SECONDARY:
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CONFIG ?= config.mk
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-include ../$(CONFIG)
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SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES))
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INC_FILES_REL = $(patsubst %, ../%, $(INC_FILES))
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XCI_FILES_REL = $(patsubst %, ../%, $(XCI_FILES))
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ifdef XDC_FILES
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XDC_FILES_REL = $(patsubst %, ../%, $(XDC_FILES))
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else
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XDC_FILES_REL = $(FPGA_TOP).xdc
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endif
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###################################################################
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# Main Targets
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#
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# all: build everything
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# clean: remove output files and project files
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###################################################################
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all: fpga
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fpga: $(FPGA_TOP).bit
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tmpclean:
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-rm -rf *.log *.jou *.cache *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v
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-rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl
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clean: tmpclean
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-rm -rf *.bit program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl
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distclean: clean
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-rm -rf rev
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###################################################################
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# Target implementations
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###################################################################
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# Vivado project file
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%.xpr: Makefile $(XCI_FILES_REL)
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rm -rf defines.v
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touch defines.v
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for x in $(DEFS); do echo '`define' $$x >> defines.v; done
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echo "create_project -force -part $(FPGA_PART) $*" > create_project.tcl
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echo "add_files -fileset sources_1 defines.v" >> create_project.tcl
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for x in $(SYN_FILES_REL); do echo "add_files -fileset sources_1 $$x" >> create_project.tcl; done
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for x in $(XDC_FILES_REL); do echo "add_files -fileset constrs_1 $$x" >> create_project.tcl; done
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for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> create_project.tcl; done
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echo "exit" >> create_project.tcl
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vivado -nojournal -nolog -mode batch -source create_project.tcl
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# synthesis run
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%.runs/synth_1/%.dcp: %.xpr $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL)
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echo "open_project $*.xpr" > run_synth.tcl
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echo "reset_run synth_1" >> run_synth.tcl
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echo "launch_runs synth_1" >> run_synth.tcl
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echo "wait_on_run synth_1" >> run_synth.tcl
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echo "exit" >> run_synth.tcl
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vivado -nojournal -nolog -mode batch -source run_synth.tcl
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# implementation run
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%.runs/impl_1/%_routed.dcp: %.runs/synth_1/%.dcp
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echo "open_project $*.xpr" > run_impl.tcl
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echo "reset_run impl_1" >> run_impl.tcl
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echo "launch_runs impl_1" >> run_impl.tcl
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echo "wait_on_run impl_1" >> run_impl.tcl
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echo "exit" >> run_impl.tcl
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vivado -nojournal -nolog -mode batch -source run_impl.tcl
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# bit file
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%.bit: %.runs/impl_1/%_routed.dcp
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echo "open_project $*.xpr" > generate_bit.tcl
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echo "open_run impl_1" >> generate_bit.tcl
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echo "write_bitstream -force $*.bit" >> generate_bit.tcl
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echo "exit" >> generate_bit.tcl
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vivado -nojournal -nolog -mode batch -source generate_bit.tcl
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mkdir -p rev
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EXT=bit; COUNT=100; \
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while [ -e rev/$*_rev$$COUNT.$$EXT ]; \
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do COUNT=$$((COUNT+1)); done; \
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cp $@ rev/$*_rev$$COUNT.$$EXT; \
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echo "Output: rev/$*_rev$$COUNT.$$EXT";
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11
example/ExaNIC_X10/fpga/driver/Makefile
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11
example/ExaNIC_X10/fpga/driver/Makefile
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# object files to build
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obj-m += example.o
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example-objs += example_driver.o
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all:
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make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules
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clean:
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make -C /lib/modules/$(shell uname -r)/build M=$(PWD) clean
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371
example/ExaNIC_X10/fpga/driver/example_driver.c
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371
example/ExaNIC_X10/fpga/driver/example_driver.c
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/*
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Copyright (c) 2018 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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#include "example_driver.h"
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/pci-aspm.h>
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#include <linux/delay.h>
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MODULE_DESCRIPTION("verilog-pcie exmaple driver");
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MODULE_AUTHOR("Alex Forencich");
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MODULE_LICENSE("Dual MIT/GPL");
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MODULE_VERSION(DRIVER_VERSION);
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MODULE_SUPPORTED_DEVICE(DRIVER_NAME);
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static int edev_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
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static void edev_remove(struct pci_dev *pdev);
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static void edev_shutdown(struct pci_dev *pdev);
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static int enumerate_bars(struct example_dev *edev, struct pci_dev *pdev);
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static int map_bars(struct example_dev *edev, struct pci_dev *pdev);
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static void free_bars(struct example_dev *edev, struct pci_dev *pdev);
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static const struct pci_device_id pci_ids[] = {
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{ PCI_DEVICE(0x1234, 0x0001) },
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{ 0 /* end */ }
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};
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MODULE_DEVICE_TABLE(pci, pci_ids);
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static irqreturn_t edev_intr(int irq, void *data)
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{
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struct example_dev *edev = data;
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struct device *dev = &edev->pdev->dev;
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edev->irqcount++;
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dev_info(dev, "Interrupt");
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return IRQ_HANDLED;
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}
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static int edev_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
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{
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int ret = 0;
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struct example_dev *edev;
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struct device *dev = &pdev->dev;
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int k;
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dev_info(dev, "edev probe");
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dev_info(dev, " vendor: 0x%04x", pdev->vendor);
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dev_info(dev, " device: 0x%04x", pdev->device);
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dev_info(dev, " class: 0x%06x", pdev->class);
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dev_info(dev, " pci id: %02x:%02x.%02x", pdev->bus->number, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
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if (!(edev = devm_kzalloc(dev, sizeof(struct example_dev), GFP_KERNEL))) {
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return -ENOMEM;
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}
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edev->pdev = pdev;
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pci_set_drvdata(pdev, edev);
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// Allocate DMA buffer
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edev->dma_region_len = 16*1024;
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edev->dma_region = dma_alloc_coherent(dev, edev->dma_region_len, &edev->dma_region_addr, GFP_KERNEL | __GFP_ZERO);
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if (!edev->dma_region)
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{
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dev_err(dev, "Failed to allocate DMA buffer");
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ret = -ENOMEM;
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goto fail_dma_alloc;
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}
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dev_info(dev, "Allocated DMA region virt %p, phys %p", edev->dma_region, (void *)edev->dma_region_addr);
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// Disable ASPM
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pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 | PCIE_LINK_STATE_CLKPM);
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// Enable device
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ret = pci_enable_device_mem(pdev);
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if (ret)
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{
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dev_err(dev, "Failed to enable PCI device");
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//ret = -ENODEV;
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goto fail_enable_device;
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}
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// Enable bus mastering for DMA
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pci_set_master(pdev);
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// Reserve regions
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ret = pci_request_regions(pdev, DRIVER_NAME);
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if (ret)
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{
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dev_err(dev, "Failed to reserve regions");
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//ret = -EBUSY;
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goto fail_regions;
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}
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// Enumerate BARs
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enumerate_bars(edev, pdev);
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// Map BARs
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ret = map_bars(edev, pdev);
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if (ret)
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{
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dev_err(dev, "Failed to map BARs");
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goto fail_map_bars;
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}
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// Allocate MSI IRQs
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ret = pci_alloc_irq_vectors(pdev, 1, 32, PCI_IRQ_MSI);
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if (ret < 0)
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{
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dev_err(dev, "Failed to allocate IRQs");
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goto fail_map_bars;
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}
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// Set up interrupt
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ret = pci_request_irq(pdev, 0, edev_intr, 0, edev, "edev");
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if (ret < 0)
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{
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dev_err(dev, "Failed to request IRQ");
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goto fail_irq;
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}
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// Dump counters
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dev_info(dev, "TLP counters");
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dev_info(dev, "RQ: %d", ioread32(edev->bar[0]+0x000400));
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dev_info(dev, "RC: %d", ioread32(edev->bar[0]+0x000404));
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dev_info(dev, "CQ: %d", ioread32(edev->bar[0]+0x000408));
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dev_info(dev, "CC: %d", ioread32(edev->bar[0]+0x00040C));
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// Read/write test
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dev_info(dev, "write to BAR1");
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iowrite32(0x11223344, edev->bar[1]);
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dev_info(dev, "read from BAR1");
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dev_info(dev, "%08x", ioread32(edev->bar[1]));
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// Dump counters
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dev_info(dev, "TLP counters");
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dev_info(dev, "RQ: %d", ioread32(edev->bar[0]+0x000400));
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dev_info(dev, "RC: %d", ioread32(edev->bar[0]+0x000404));
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dev_info(dev, "CQ: %d", ioread32(edev->bar[0]+0x000408));
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dev_info(dev, "CC: %d", ioread32(edev->bar[0]+0x00040C));
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// PCIe DMA test
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dev_info(dev, "write test data");
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for (k = 0; k < 256; k++)
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{
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((char *)edev->dma_region)[k] = k;
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}
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||||||
|
dev_info(dev, "read test data");
|
||||||
|
print_hex_dump(KERN_INFO, "", DUMP_PREFIX_NONE, 16, 1, edev->dma_region, 256, true);
|
||||||
|
|
||||||
|
dev_info(dev, "check DMA enable");
|
||||||
|
dev_info(dev, "%08x", ioread32(edev->bar[0]+0x000000));
|
||||||
|
|
||||||
|
dev_info(dev, "enable DMA");
|
||||||
|
iowrite32(0x1, edev->bar[0]+0x000000);
|
||||||
|
|
||||||
|
dev_info(dev, "check DMA enable");
|
||||||
|
dev_info(dev, "%08x", ioread32(edev->bar[0]+0x000000));
|
||||||
|
|
||||||
|
dev_info(dev, "start copy to card");
|
||||||
|
iowrite32((edev->dma_region_addr+0x0000)&0xffffffff, edev->bar[0]+0x000100);
|
||||||
|
iowrite32(((edev->dma_region_addr+0x0000) >> 32)&0xffffffff, edev->bar[0]+0x000104);
|
||||||
|
iowrite32(0x100, edev->bar[0]+0x000108);
|
||||||
|
iowrite32(0, edev->bar[0]+0x00010C);
|
||||||
|
iowrite32(0x100, edev->bar[0]+0x000110);
|
||||||
|
iowrite32(0xAA, edev->bar[0]+0x000114);
|
||||||
|
|
||||||
|
msleep(1);
|
||||||
|
|
||||||
|
dev_info(dev, "Read status");
|
||||||
|
dev_info(dev, "%08x", ioread32(edev->bar[0]+0x000118));
|
||||||
|
|
||||||
|
dev_info(dev, "start copy to host");
|
||||||
|
iowrite32((edev->dma_region_addr+0x0200)&0xffffffff, edev->bar[0]+0x000200);
|
||||||
|
iowrite32(((edev->dma_region_addr+0x0200) >> 32)&0xffffffff, edev->bar[0]+0x000204);
|
||||||
|
iowrite32(0x100, edev->bar[0]+0x000208);
|
||||||
|
iowrite32(0, edev->bar[0]+0x00020C);
|
||||||
|
iowrite32(0x100, edev->bar[0]+0x000210);
|
||||||
|
iowrite32(0x55, edev->bar[0]+0x000214);
|
||||||
|
|
||||||
|
msleep(1);
|
||||||
|
|
||||||
|
dev_info(dev, "Read status");
|
||||||
|
dev_info(dev, "%08x", ioread32(edev->bar[0]+0x000218));
|
||||||
|
|
||||||
|
dev_info(dev, "read test data");
|
||||||
|
print_hex_dump(KERN_INFO, "", DUMP_PREFIX_NONE, 16, 1, edev->dma_region+0x0200, 256, true);
|
||||||
|
|
||||||
|
// Dump counters
|
||||||
|
dev_info(dev, "TLP counters");
|
||||||
|
dev_info(dev, "RQ: %d", ioread32(edev->bar[0]+0x000400));
|
||||||
|
dev_info(dev, "RC: %d", ioread32(edev->bar[0]+0x000404));
|
||||||
|
dev_info(dev, "CQ: %d", ioread32(edev->bar[0]+0x000408));
|
||||||
|
dev_info(dev, "CC: %d", ioread32(edev->bar[0]+0x00040C));
|
||||||
|
|
||||||
|
// probe complete
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
// error handling
|
||||||
|
fail_irq:
|
||||||
|
pci_free_irq_vectors(pdev);
|
||||||
|
fail_map_bars:
|
||||||
|
free_bars(edev, pdev);
|
||||||
|
pci_release_regions(pdev);
|
||||||
|
fail_regions:
|
||||||
|
pci_clear_master(pdev);
|
||||||
|
pci_disable_device(pdev);
|
||||||
|
fail_enable_device:
|
||||||
|
dma_free_coherent(dev, edev->dma_region_len, edev->dma_region, edev->dma_region_addr);
|
||||||
|
fail_dma_alloc:
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void edev_remove(struct pci_dev *pdev)
|
||||||
|
{
|
||||||
|
struct example_dev *edev;
|
||||||
|
struct device *dev = &pdev->dev;
|
||||||
|
|
||||||
|
dev_info(dev, "edev remove");
|
||||||
|
|
||||||
|
if (!(edev = pci_get_drvdata(pdev))) {
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
pci_free_irq(pdev, 0, edev);
|
||||||
|
pci_free_irq_vectors(pdev);
|
||||||
|
free_bars(edev, pdev);
|
||||||
|
pci_release_regions(pdev);
|
||||||
|
pci_clear_master(pdev);
|
||||||
|
pci_disable_device(pdev);
|
||||||
|
dma_free_coherent(dev, edev->dma_region_len, edev->dma_region, edev->dma_region_addr);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void edev_shutdown(struct pci_dev *pdev)
|
||||||
|
{
|
||||||
|
struct example_dev *edev = pci_get_drvdata(pdev);
|
||||||
|
struct device *dev = &pdev->dev;
|
||||||
|
|
||||||
|
dev_info(dev, "edev shutdown");
|
||||||
|
|
||||||
|
if (!edev) {
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
// ensure DMA is disabled on shutdown
|
||||||
|
pci_clear_master(pdev);
|
||||||
|
}
|
||||||
|
|
||||||
|
static int enumerate_bars(struct example_dev *edev, struct pci_dev *pdev)
|
||||||
|
{
|
||||||
|
struct device *dev = &pdev->dev;
|
||||||
|
int i;
|
||||||
|
|
||||||
|
for (i = 0; i < DEV_BAR_CNT; i++)
|
||||||
|
{
|
||||||
|
resource_size_t bar_start = pci_resource_start(pdev, i);
|
||||||
|
if (bar_start)
|
||||||
|
{
|
||||||
|
resource_size_t bar_end = pci_resource_end(pdev, i);
|
||||||
|
unsigned long bar_flags = pci_resource_flags(pdev, i);
|
||||||
|
dev_info(dev, "BAR[%d] 0x%08llx-0x%08llx flags 0x%08lx",
|
||||||
|
i, bar_start, bar_end, bar_flags);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int map_bars(struct example_dev *edev, struct pci_dev *pdev)
|
||||||
|
{
|
||||||
|
struct device *dev = &pdev->dev;
|
||||||
|
int i;
|
||||||
|
|
||||||
|
for (i = 0; i < DEV_BAR_CNT; i++)
|
||||||
|
{
|
||||||
|
resource_size_t bar_start = pci_resource_start(pdev, i);
|
||||||
|
resource_size_t bar_end = pci_resource_end(pdev, i);
|
||||||
|
resource_size_t bar_len = bar_end - bar_start + 1;
|
||||||
|
edev->bar_len[i] = bar_len;
|
||||||
|
|
||||||
|
if (!bar_start || !bar_end)
|
||||||
|
{
|
||||||
|
edev->bar_len[i] = 0;
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (bar_len < 1)
|
||||||
|
{
|
||||||
|
dev_warn(dev, "BAR[%d] is less than 1 byte", i);
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
|
||||||
|
edev->bar[i] = pci_ioremap_bar(pdev, i);
|
||||||
|
|
||||||
|
if (!edev->bar[i])
|
||||||
|
{
|
||||||
|
dev_err(dev, "Could not map BAR[%d]", i);
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
dev_info(dev, "BAR[%d] mapped at 0x%p with length %llu", i, edev->bar[i], bar_len);
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void free_bars(struct example_dev *edev, struct pci_dev *pdev)
|
||||||
|
{
|
||||||
|
struct device *dev = &pdev->dev;
|
||||||
|
int i;
|
||||||
|
|
||||||
|
for (i = 0; i < DEV_BAR_CNT; i++)
|
||||||
|
{
|
||||||
|
if (edev->bar[i])
|
||||||
|
{
|
||||||
|
pci_iounmap(pdev, edev->bar[i]);
|
||||||
|
edev->bar[i] = NULL;
|
||||||
|
dev_info(dev, "Unmapped BAR[%d]", i);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static struct pci_driver pci_driver = {
|
||||||
|
.name = DRIVER_NAME,
|
||||||
|
.id_table = pci_ids,
|
||||||
|
.probe = edev_probe,
|
||||||
|
.remove = edev_remove,
|
||||||
|
.shutdown = edev_shutdown
|
||||||
|
};
|
||||||
|
|
||||||
|
static int __init edev_init(void)
|
||||||
|
{
|
||||||
|
return pci_register_driver(&pci_driver);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void __exit edev_exit(void)
|
||||||
|
{
|
||||||
|
pci_unregister_driver(&pci_driver);
|
||||||
|
}
|
||||||
|
|
||||||
|
module_init(edev_init);
|
||||||
|
module_exit(edev_exit);
|
||||||
|
|
||||||
50
example/ExaNIC_X10/fpga/driver/example_driver.h
Normal file
50
example/ExaNIC_X10/fpga/driver/example_driver.h
Normal file
@ -0,0 +1,50 @@
|
|||||||
|
/*
|
||||||
|
|
||||||
|
Copyright (c) 2018 Alex Forencich
|
||||||
|
|
||||||
|
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||||
|
of this software and associated documentation files (the "Software"), to deal
|
||||||
|
in the Software without restriction, including without limitation the rights
|
||||||
|
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||||
|
copies of the Software, and to permit persons to whom the Software is
|
||||||
|
furnished to do so, subject to the following conditions:
|
||||||
|
|
||||||
|
The above copyright notice and this permission notice shall be included in
|
||||||
|
all copies or substantial portions of the Software.
|
||||||
|
|
||||||
|
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||||
|
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||||
|
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||||
|
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||||
|
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||||
|
THE SOFTWARE.
|
||||||
|
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef EXAMPLE_DRIVER_H
|
||||||
|
#define EXAMPLE_DRIVER_H
|
||||||
|
|
||||||
|
#include <linux/kernel.h>
|
||||||
|
|
||||||
|
#define DRIVER_NAME "edev"
|
||||||
|
#define DRIVER_VERSION "0.1"
|
||||||
|
|
||||||
|
#define DEV_BAR_CNT 2
|
||||||
|
|
||||||
|
struct example_dev {
|
||||||
|
struct pci_dev *pdev;
|
||||||
|
|
||||||
|
// BAR pointers
|
||||||
|
void * __iomem bar[DEV_BAR_CNT];
|
||||||
|
resource_size_t bar_len[DEV_BAR_CNT];
|
||||||
|
|
||||||
|
// DMA buffer
|
||||||
|
size_t dma_region_len;
|
||||||
|
void *dma_region;
|
||||||
|
dma_addr_t dma_region_addr;
|
||||||
|
|
||||||
|
int irqcount;
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif /* EXAMPLE_DRIVER_H */
|
||||||
153
example/ExaNIC_X10/fpga/fpga.xdc
Normal file
153
example/ExaNIC_X10/fpga/fpga.xdc
Normal file
@ -0,0 +1,153 @@
|
|||||||
|
# XDC constraints for the ExaNIC X10
|
||||||
|
# part: xcku035-fbva676-2-e
|
||||||
|
|
||||||
|
# General configuration
|
||||||
|
set_property CFGBVS GND [current_design]
|
||||||
|
set_property CONFIG_VOLTAGE 1.8 [current_design]
|
||||||
|
set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
|
||||||
|
set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design]
|
||||||
|
set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]
|
||||||
|
set_property BITSTREAM.CONFIG.BPI_SYNC_MODE Type2 [current_design]
|
||||||
|
set_property CONFIG_MODE BPI16 [current_design]
|
||||||
|
|
||||||
|
# 100 MHz system clock
|
||||||
|
#set_property -dict {LOC D18 IOSTANDARD LVDS} [get_ports clk_100mhz_p]
|
||||||
|
#set_property -dict {LOC C18 IOSTANDARD LVDS} [get_ports clk_100mhz_n]
|
||||||
|
#create_clock -period 10 -name clk_100mhz [get_ports clk_100mhz_p]
|
||||||
|
|
||||||
|
# LEDs
|
||||||
|
set_property -dict {LOC A25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_1_led[0]}]
|
||||||
|
set_property -dict {LOC A24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_1_led[1]}]
|
||||||
|
set_property -dict {LOC E23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_2_led[0]}]
|
||||||
|
set_property -dict {LOC D26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_2_led[1]}]
|
||||||
|
set_property -dict {LOC C23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sma_led[0]}]
|
||||||
|
set_property -dict {LOC D23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sma_led[1]}]
|
||||||
|
|
||||||
|
# GPIO
|
||||||
|
#set_property -dict {LOC W26 IOSTANDARD LVCMOS18} [get_ports gpio[0]]
|
||||||
|
#set_property -dict {LOC Y26 IOSTANDARD LVCMOS18} [get_ports gpio[1]]
|
||||||
|
#set_property -dict {LOC AB26 IOSTANDARD LVCMOS18} [get_ports gpio[2]]
|
||||||
|
#set_property -dict {LOC AC26 IOSTANDARD LVCMOS18} [get_ports gpio[3]]
|
||||||
|
|
||||||
|
# SMA
|
||||||
|
#set_property -dict {LOC B17 IOSTANDARD LVCMOS18} [get_ports sma_in]
|
||||||
|
#set_property -dict {LOC B16 IOSTANDARD LVCMOS18} [get_ports sma_out]
|
||||||
|
#set_property -dict {LOC B19 IOSTANDARD LVCMOS18} [get_ports sma_out_en]
|
||||||
|
#set_property -dict {LOC C16 IOSTANDARD LVCMOS18} [get_ports sma_term_en]
|
||||||
|
|
||||||
|
# SFP+ Interface
|
||||||
|
#set_property -dict {LOC D2 } [get_ports sfp_1_rx_p] ;# MGTHTXN0_227 GTHE3_CHANNEL_X0Y12 / GTHE3_COMMON_X0Y3
|
||||||
|
#set_property -dict {LOC D1 } [get_ports sfp_1_rx_n] ;# MGTHTXP0_227 GTHE3_CHANNEL_X0Y12 / GTHE3_COMMON_X0Y3
|
||||||
|
#set_property -dict {LOC E4 } [get_ports sfp_1_tx_p] ;# MGTHTXN0_227 GTHE3_CHANNEL_X0Y12 / GTHE3_COMMON_X0Y3
|
||||||
|
#set_property -dict {LOC E3 } [get_ports sfp_1_tx_n] ;# MGTHTXP0_227 GTHE3_CHANNEL_X0Y12 / GTHE3_COMMON_X0Y3
|
||||||
|
#set_property -dict {LOC C4 } [get_ports sfp_2_rx_p] ;# MGTHTXN1_227 GTHE3_CHANNEL_X0Y13 / GTHE3_COMMON_X0Y3
|
||||||
|
#set_property -dict {LOC C3 } [get_ports sfp_2_rx_n] ;# MGTHTXP1_227 GTHE3_CHANNEL_X0Y13 / GTHE3_COMMON_X0Y3
|
||||||
|
#set_property -dict {LOC D6 } [get_ports sfp_2_tx_p] ;# MGTHTXN1_227 GTHE3_CHANNEL_X0Y13 / GTHE3_COMMON_X0Y3
|
||||||
|
#set_property -dict {LOC D5 } [get_ports sfp_2_tx_n] ;# MGTHTXP1_227 GTHE3_CHANNEL_X0Y13 / GTHE3_COMMON_X0Y3
|
||||||
|
#set_property -dict {LOC H6 } [get_ports sfp_mgt_refclk_p] ;# MGTREFCLK0P_227 from X2
|
||||||
|
#set_property -dict {LOC H5 } [get_ports sfp_mgt_refclk_n] ;# MGTREFCLK0N_227 from X2
|
||||||
|
#set_property -dict {LOC AA12 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports sfp_1_tx_disable]
|
||||||
|
#set_property -dict {LOC W14 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports sfp_2_tx_disable]
|
||||||
|
#set_property -dict {LOC C24 IOSTANDARD LVCMOS18 PULLUP true} [get_ports sfp_1_npres]
|
||||||
|
#set_property -dict {LOC D24 IOSTANDARD LVCMOS18 PULLUP true} [get_ports sfp_2_npres]
|
||||||
|
#set_property -dict {LOC W13 IOSTANDARD LVCMOS18 PULLUP true} [get_ports sfp_1_los]
|
||||||
|
#set_property -dict {LOC AB12 IOSTANDARD LVCMOS18 PULLUP true} [get_ports sfp_2_los]
|
||||||
|
#set_property -dict {LOC B25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports sfp_1_rs]
|
||||||
|
#set_property -dict {LOC D25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports sfp_2_rs]
|
||||||
|
#set_property -dict {LOC W11 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports sfp_i2c_scl]
|
||||||
|
#set_property -dict {LOC Y11 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports sfp_1_i2c_sda]
|
||||||
|
#set_property -dict {LOC Y13 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports sfp_2_i2c_sda]
|
||||||
|
|
||||||
|
# 161.1328125 MHz MGT reference clock
|
||||||
|
#create_clock -period 6.206 -name sfp_mgt_refclk [get_ports sfp_mgt_refclk_p]
|
||||||
|
|
||||||
|
# I2C interface
|
||||||
|
#set_property -dict {LOC B26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports eeprom_i2c_scl]
|
||||||
|
#set_property -dict {LOC C26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports eeprom_i2c_sda]
|
||||||
|
|
||||||
|
# PCIe Interface
|
||||||
|
set_property -dict {LOC AF2 } [get_ports {pcie_rx_p[7]}] ;# MGTHTXN0_224 GTHE3_CHANNEL_X0Y0 / GTHE3_COMMON_X0Y0
|
||||||
|
#set_property -dict {LOC AF1 } [get_ports {pcie_rx_n[7]}] ;# MGTHTXP0_224 GTHE3_CHANNEL_X0Y0 / GTHE3_COMMON_X0Y0
|
||||||
|
set_property -dict {LOC AF6 } [get_ports {pcie_tx_p[7]}] ;# MGTHTXN0_224 GTHE3_CHANNEL_X0Y0 / GTHE3_COMMON_X0Y0
|
||||||
|
#set_property -dict {LOC AF5 } [get_ports {pcie_tx_n[7]}] ;# MGTHTXP0_224 GTHE3_CHANNEL_X0Y0 / GTHE3_COMMON_X0Y0
|
||||||
|
set_property -dict {LOC AE4 } [get_ports {pcie_rx_p[6]}] ;# MGTHTXN1_224 GTHE3_CHANNEL_X0Y1 / GTHE3_COMMON_X0Y0
|
||||||
|
#set_property -dict {LOC AE3 } [get_ports {pcie_rx_n[6]}] ;# MGTHTXP1_224 GTHE3_CHANNEL_X0Y1 / GTHE3_COMMON_X0Y0
|
||||||
|
set_property -dict {LOC AD6 } [get_ports {pcie_tx_p[6]}] ;# MGTHTXN1_224 GTHE3_CHANNEL_X0Y1 / GTHE3_COMMON_X0Y0
|
||||||
|
#set_property -dict {LOC AD5 } [get_ports {pcie_tx_n[6]}] ;# MGTHTXP1_224 GTHE3_CHANNEL_X0Y1 / GTHE3_COMMON_X0Y0
|
||||||
|
set_property -dict {LOC AD2 } [get_ports {pcie_rx_p[5]}] ;# MGTHTXN2_224 GTHE3_CHANNEL_X0Y2 / GTHE3_COMMON_X0Y0
|
||||||
|
#set_property -dict {LOC AD1 } [get_ports {pcie_rx_n[5]}] ;# MGTHTXP2_224 GTHE3_CHANNEL_X0Y2 / GTHE3_COMMON_X0Y0
|
||||||
|
set_property -dict {LOC AC4 } [get_ports {pcie_tx_p[5]}] ;# MGTHTXN2_224 GTHE3_CHANNEL_X0Y2 / GTHE3_COMMON_X0Y0
|
||||||
|
#set_property -dict {LOC AC3 } [get_ports {pcie_tx_n[5]}] ;# MGTHTXP2_224 GTHE3_CHANNEL_X0Y2 / GTHE3_COMMON_X0Y0
|
||||||
|
set_property -dict {LOC AB2 } [get_ports {pcie_rx_p[4]}] ;# MGTHTXN3_224 GTHE3_CHANNEL_X0Y3 / GTHE3_COMMON_X0Y0
|
||||||
|
#set_property -dict {LOC AB1 } [get_ports {pcie_rx_n[4]}] ;# MGTHTXP3_224 GTHE3_CHANNEL_X0Y3 / GTHE3_COMMON_X0Y0
|
||||||
|
set_property -dict {LOC AB6 } [get_ports {pcie_tx_p[4]}] ;# MGTHTXN3_224 GTHE3_CHANNEL_X0Y3 / GTHE3_COMMON_X0Y0
|
||||||
|
#set_property -dict {LOC AB5 } [get_ports {pcie_tx_n[4]}] ;# MGTHTXP3_224 GTHE3_CHANNEL_X0Y3 / GTHE3_COMMON_X0Y0
|
||||||
|
set_property -dict {LOC Y2 } [get_ports {pcie_rx_p[3]}] ;# MGTHTXN0_225 GTHE3_CHANNEL_X0Y4 / GTHE3_COMMON_X0Y1
|
||||||
|
#set_property -dict {LOC Y1 } [get_ports {pcie_rx_n[3]}] ;# MGTHTXP0_225 GTHE3_CHANNEL_X0Y4 / GTHE3_COMMON_X0Y1
|
||||||
|
set_property -dict {LOC AA4 } [get_ports {pcie_tx_p[3]}] ;# MGTHTXN0_225 GTHE3_CHANNEL_X0Y4 / GTHE3_COMMON_X0Y1
|
||||||
|
#set_property -dict {LOC AA3 } [get_ports {pcie_tx_n[3]}] ;# MGTHTXP0_225 GTHE3_CHANNEL_X0Y4 / GTHE3_COMMON_X0Y1
|
||||||
|
set_property -dict {LOC V2 } [get_ports {pcie_rx_p[2]}] ;# MGTHTXN1_225 GTHE3_CHANNEL_X0Y5 / GTHE3_COMMON_X0Y1
|
||||||
|
#set_property -dict {LOC V1 } [get_ports {pcie_rx_n[2]}] ;# MGTHTXP1_225 GTHE3_CHANNEL_X0Y5 / GTHE3_COMMON_X0Y1
|
||||||
|
set_property -dict {LOC W4 } [get_ports {pcie_tx_p[2]}] ;# MGTHTXN1_225 GTHE3_CHANNEL_X0Y5 / GTHE3_COMMON_X0Y1
|
||||||
|
#set_property -dict {LOC W3 } [get_ports {pcie_tx_n[2]}] ;# MGTHTXP1_225 GTHE3_CHANNEL_X0Y5 / GTHE3_COMMON_X0Y1
|
||||||
|
set_property -dict {LOC T2 } [get_ports {pcie_rx_p[1]}] ;# MGTHTXN2_225 GTHE3_CHANNEL_X0Y6 / GTHE3_COMMON_X0Y1
|
||||||
|
#set_property -dict {LOC T1 } [get_ports {pcie_rx_n[1]}] ;# MGTHTXP2_225 GTHE3_CHANNEL_X0Y6 / GTHE3_COMMON_X0Y1
|
||||||
|
set_property -dict {LOC U4 } [get_ports {pcie_tx_p[1]}] ;# MGTHTXN2_225 GTHE3_CHANNEL_X0Y6 / GTHE3_COMMON_X0Y1
|
||||||
|
#set_property -dict {LOC U3 } [get_ports {pcie_tx_n[1]}] ;# MGTHTXP2_225 GTHE3_CHANNEL_X0Y6 / GTHE3_COMMON_X0Y1
|
||||||
|
set_property -dict {LOC P2 } [get_ports {pcie_rx_p[0]}] ;# MGTHTXN3_225 GTHE3_CHANNEL_X0Y7 / GTHE3_COMMON_X0Y1
|
||||||
|
#set_property -dict {LOC P1 } [get_ports {pcie_rx_n[0]}] ;# MGTHTXP3_225 GTHE3_CHANNEL_X0Y7 / GTHE3_COMMON_X0Y1
|
||||||
|
set_property -dict {LOC R4 } [get_ports {pcie_tx_p[0]}] ;# MGTHTXN3_225 GTHE3_CHANNEL_X0Y7 / GTHE3_COMMON_X0Y1
|
||||||
|
#set_property -dict {LOC R3 } [get_ports {pcie_tx_n[0]}] ;# MGTHTXP3_225 GTHE3_CHANNEL_X0Y7 / GTHE3_COMMON_X0Y1
|
||||||
|
set_property -dict {LOC T6 } [get_ports pcie_mgt_refclk_p] ;# MGTREFCLK0P_225
|
||||||
|
#set_property -dict {LOC T5 } [get_ports pcie_mgt_refclk_n] ;# MGTREFCLK0N_225
|
||||||
|
set_property -dict {LOC AC22 IOSTANDARD LVCMOS18 PULLUP true} [get_ports pcie_reset_n]
|
||||||
|
|
||||||
|
# 100 MHz MGT reference clock
|
||||||
|
create_clock -period 10 -name pcie_mgt_refclk [get_ports pcie_mgt_refclk_p]
|
||||||
|
|
||||||
|
# Flash
|
||||||
|
#set_property -dict {LOC AE10 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[0]}]
|
||||||
|
#set_property -dict {LOC AC8 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[1]}]
|
||||||
|
#set_property -dict {LOC AD10 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[2]}]
|
||||||
|
#set_property -dict {LOC AD9 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[3]}]
|
||||||
|
#set_property -dict {LOC AC11 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[4]}]
|
||||||
|
#set_property -dict {LOC AF10 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[5]}]
|
||||||
|
#set_property -dict {LOC AF14 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[6]}]
|
||||||
|
#set_property -dict {LOC AE12 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[7]}]
|
||||||
|
#set_property -dict {LOC AD14 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[8]}]
|
||||||
|
#set_property -dict {LOC AF13 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[9]}]
|
||||||
|
#set_property -dict {LOC AE13 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[10]}]
|
||||||
|
#set_property -dict {LOC AD8 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[11]}]
|
||||||
|
#set_property -dict {LOC AC13 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[12]}]
|
||||||
|
#set_property -dict {LOC AD13 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[13]}]
|
||||||
|
#set_property -dict {LOC AA14 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[14]}]
|
||||||
|
#set_property -dict {LOC AB15 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[15]}]
|
||||||
|
#set_property -dict {LOC AD11 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[0]}]
|
||||||
|
#set_property -dict {LOC AE11 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[1]}]
|
||||||
|
#set_property -dict {LOC AF12 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[2]}]
|
||||||
|
#set_property -dict {LOC AB11 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[3]}]
|
||||||
|
#set_property -dict {LOC AB9 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[4]}]
|
||||||
|
#set_property -dict {LOC AB14 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[5]}]
|
||||||
|
#set_property -dict {LOC AA10 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[6]}]
|
||||||
|
#set_property -dict {LOC AA9 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[7]}]
|
||||||
|
#set_property -dict {LOC W10 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[8]}]
|
||||||
|
#set_property -dict {LOC AA13 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[9]}]
|
||||||
|
#set_property -dict {LOC Y15 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[10]}]
|
||||||
|
#set_property -dict {LOC AC12 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[11]}]
|
||||||
|
#set_property -dict {LOC V12 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[12]}]
|
||||||
|
#set_property -dict {LOC V11 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[13]}]
|
||||||
|
#set_property -dict {LOC Y12 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[14]}]
|
||||||
|
#set_property -dict {LOC W9 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[15]}]
|
||||||
|
#set_property -dict {LOC Y8 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[16]}]
|
||||||
|
#set_property -dict {LOC W8 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[17]}]
|
||||||
|
#set_property -dict {LOC W15 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[18]}]
|
||||||
|
#set_property -dict {LOC AA15 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[19]}]
|
||||||
|
#set_property -dict {LOC AE16 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[20]}]
|
||||||
|
#set_property -dict {LOC AF15 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[21]}]
|
||||||
|
#set_property -dict {LOC AE15 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[22]}]
|
||||||
|
#set_property -dict {LOC AD15 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {flash_region}]
|
||||||
|
#set_property -dict {LOC AC9 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_ce_n}]
|
||||||
|
#set_property -dict {LOC AC14 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_oe_n}]
|
||||||
|
#set_property -dict {LOC AB10 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_we_n}]
|
||||||
|
#set_property -dict {LOC Y10 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_adv_n}]
|
||||||
|
|
||||||
87
example/ExaNIC_X10/fpga/fpga/Makefile
Normal file
87
example/ExaNIC_X10/fpga/fpga/Makefile
Normal file
@ -0,0 +1,87 @@
|
|||||||
|
|
||||||
|
# FPGA settings
|
||||||
|
FPGA_PART = xcku035-fbva676-2-e
|
||||||
|
FPGA_TOP = fpga
|
||||||
|
FPGA_ARCH = kintexu
|
||||||
|
|
||||||
|
# Files for synthesis
|
||||||
|
SYN_FILES = rtl/fpga.v
|
||||||
|
SYN_FILES += rtl/fpga_core.v
|
||||||
|
SYN_FILES += rtl/debounce_switch.v
|
||||||
|
SYN_FILES += rtl/sync_reset.v
|
||||||
|
SYN_FILES += rtl/sync_signal.v
|
||||||
|
SYN_FILES += rtl/axi_ram.v
|
||||||
|
SYN_FILES += rtl/axis_register.v
|
||||||
|
SYN_FILES += lib/pcie/rtl/axis_arb_mux.v
|
||||||
|
SYN_FILES += lib/pcie/rtl/pcie_us_axil_master.v
|
||||||
|
SYN_FILES += lib/pcie/rtl/pcie_us_axi_dma.v
|
||||||
|
SYN_FILES += lib/pcie/rtl/pcie_us_axi_dma_rd.v
|
||||||
|
SYN_FILES += lib/pcie/rtl/pcie_us_axi_dma_wr.v
|
||||||
|
SYN_FILES += lib/pcie/rtl/pcie_tag_manager.v
|
||||||
|
SYN_FILES += lib/pcie/rtl/pcie_us_axi_master.v
|
||||||
|
SYN_FILES += lib/pcie/rtl/pcie_us_axi_master_rd.v
|
||||||
|
SYN_FILES += lib/pcie/rtl/pcie_us_axi_master_wr.v
|
||||||
|
SYN_FILES += lib/pcie/rtl/pcie_us_axis_cq_demux.v
|
||||||
|
SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
|
||||||
|
SYN_FILES += lib/pcie/rtl/pcie_us_msi.v
|
||||||
|
SYN_FILES += lib/pcie/rtl/arbiter.v
|
||||||
|
SYN_FILES += lib/pcie/rtl/priority_encoder.v
|
||||||
|
SYN_FILES += lib/pcie/rtl/pulse_merge.v
|
||||||
|
|
||||||
|
# XDC files
|
||||||
|
XDC_FILES = fpga.xdc
|
||||||
|
|
||||||
|
# IP
|
||||||
|
XCI_FILES = ip/pcie3_ultrascale_0.xci
|
||||||
|
|
||||||
|
include ../common/vivado.mk
|
||||||
|
|
||||||
|
program: $(FPGA_TOP).bit
|
||||||
|
echo "open_hw" > program.tcl
|
||||||
|
echo "connect_hw_server" >> program.tcl
|
||||||
|
echo "open_hw_target" >> program.tcl
|
||||||
|
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
|
||||||
|
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
|
||||||
|
echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl
|
||||||
|
echo "program_hw_devices [current_hw_device]" >> program.tcl
|
||||||
|
echo "exit" >> program.tcl
|
||||||
|
vivado -nojournal -nolog -mode batch -source program.tcl
|
||||||
|
|
||||||
|
%.mcs %.prm: %.bit
|
||||||
|
echo "write_cfgmem -force -format mcs -size 32 -interface BPIx16 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
|
||||||
|
echo "exit" >> generate_mcs.tcl
|
||||||
|
vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
|
||||||
|
mkdir -p rev
|
||||||
|
COUNT=100; \
|
||||||
|
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||||
|
do COUNT=$$((COUNT+1)); done; \
|
||||||
|
COUNT=$$((COUNT-1)); \
|
||||||
|
for x in .mcs .prm; \
|
||||||
|
do cp $*$$x rev/$*_rev$$COUNT$$x; \
|
||||||
|
echo "Output: rev/$*_rev$$COUNT$$x"; done;
|
||||||
|
|
||||||
|
flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm
|
||||||
|
echo "open_hw" > flash.tcl
|
||||||
|
echo "connect_hw_server" >> flash.tcl
|
||||||
|
echo "open_hw_target" >> flash.tcl
|
||||||
|
echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
|
||||||
|
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
|
||||||
|
echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {28f256p30t-bpi-x16}] 0]" >> flash.tcl
|
||||||
|
echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP).mcs\"] [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP).prm\"] [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.BPI_RS_PINS {none} [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
|
||||||
|
echo "program_hw_devices [current_hw_device]" >> flash.tcl
|
||||||
|
echo "refresh_hw_device [current_hw_device]" >> flash.tcl
|
||||||
|
echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "boot_hw_device [current_hw_device]" >> flash.tcl
|
||||||
|
echo "exit" >> flash.tcl
|
||||||
|
vivado -nojournal -nolog -mode batch -source flash.tcl
|
||||||
|
|
||||||
899
example/ExaNIC_X10/fpga/ip/pcie3_ultrascale_0.xci
Normal file
899
example/ExaNIC_X10/fpga/ip/pcie3_ultrascale_0.xci
Normal file
@ -0,0 +1,899 @@
|
|||||||
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
|
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||||
|
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||||
|
<spirit:library>xci</spirit:library>
|
||||||
|
<spirit:name>unknown</spirit:name>
|
||||||
|
<spirit:version>1.0</spirit:version>
|
||||||
|
<spirit:componentInstances>
|
||||||
|
<spirit:componentInstance>
|
||||||
|
<spirit:instanceName>pcie3_ultrascale_0</spirit:instanceName>
|
||||||
|
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="pcie3_ultrascale" spirit:version="4.4"/>
|
||||||
|
<spirit:configurableElementValues>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.SYS_CLK.ASSOCIATED_BUSIF"/>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.SYS_CLK.ASSOCIATED_RESET"/>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.SYS_CLK.CLK_DOMAIN"/>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.SYS_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.SYS_CLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.SYS_CLK.PHASE">0.000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.SYS_CLK_GT.ASSOCIATED_BUSIF"/>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.SYS_CLK_GT.ASSOCIATED_RESET"/>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.SYS_CLK_GT.CLK_DOMAIN"/>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.SYS_CLK_GT.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.SYS_CLK_GT.INSERT_VIP">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.SYS_CLK_GT.PHASE">0.000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.USER_CLK.CLK_DOMAIN"/>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.USER_CLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.USER_CLK.PHASE">0.000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.CLK_DOMAIN"/>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.HAS_TKEEP">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.HAS_TLAST">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.HAS_TREADY">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.INSERT_VIP">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.PHASE">0.000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.TDATA_NUM_BYTES">32</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.TID_WIDTH">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.TUSER_WIDTH">85</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.CLK_DOMAIN"/>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.HAS_TKEEP">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.HAS_TLAST">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.HAS_TREADY">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.INSERT_VIP">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.PHASE">0.000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.TDATA_NUM_BYTES">32</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.TID_WIDTH">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.TUSER_WIDTH">75</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.SYS_RST.INSERT_VIP">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.SYS_RST.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.USER_RESET.INSERT_VIP">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.CLK_DOMAIN"/>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.HAS_TKEEP">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.HAS_TLAST">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.HAS_TREADY">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.INSERT_VIP">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.PHASE">0.000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.TDATA_NUM_BYTES">32</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.TID_WIDTH">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.TUSER_WIDTH">33</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.CLK_DOMAIN"/>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.HAS_TKEEP">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.HAS_TLAST">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.HAS_TREADY">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.INSERT_VIP">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.PHASE">0.000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.TDATA_NUM_BYTES">32</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.TID_WIDTH">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.TUSER_WIDTH">60</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ACS_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ACS_EXT_CAP_ENABLE">FALSE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ARI_CAP_ENABLE">FALSE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXISTEN_IF_CC_ALIGNMENT_MODE">FALSE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXISTEN_IF_CC_PARITY_CHK">FALSE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXISTEN_IF_CQ_ALIGNMENT_MODE">FALSE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXISTEN_IF_ENABLE_CLIENT_TAG">TRUE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXISTEN_IF_ENABLE_MSG_ROUTE">0x00000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXISTEN_IF_ENABLE_RX_MSG_INTFC">FALSE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXISTEN_IF_RC_ALIGNMENT_MODE">FALSE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXISTEN_IF_RC_STRADDLE">FALSE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXISTEN_IF_RQ_ALIGNMENT_MODE">FALSE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXISTEN_IF_RQ_PARITY_CHK">FALSE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.BMD_PIO_MODE">FALSE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CFG_CTL_IF">TRUE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CFG_EXT_IF">TRUE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CFG_FC_IF">TRUE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CFG_MGMT_IF">TRUE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CFG_STATUS_IF">TRUE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CFG_TX_MSG_IF">TRUE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.COMPLETION_SPACE">16KB</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CORE_CLK_FREQ">2</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_WIDTH">256</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DBG_DESCRAMBLE_EN">FALSE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DEDICATE_PERST">TRUE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DEV_PORT_TYPE">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DIS_GT_WIZARD">FALSE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ENABLE_AUTO_RXEQ">FALSE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ENABLE_GT_V1_5">FALSE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ENABLE_IBERT">FALSE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ENABLE_JTAG_DBG">FALSE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.EN_GT_SELECTION">FALSE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.EXT_CH_GT_DRP">FALSE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.EXT_STARTUP_PRIMITIVE">FALSE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.EXT_XVC_VSEC_ENABLE">FALSE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.FREE_RUN_FREQ">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.GTWIZ_IN_CORE">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.GT_DRP_CLK_SRC">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.INS_LOSS_PROFILE">Add-in_Card</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MCAP_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MCAP_ENABLEMENT">NONE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MCAP_FPGA_BITSTREAM_VERSION">0x00000000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MSIX_EN">FALSE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MSI_EN">TRUE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MULT_PF_DES">FALSE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PCIE3_DRP">FALSE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PCIE_CONFIGURATION">FALSE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PCIE_FAST_CONFIG">NONE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PCIE_LINK_SPEED">3</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PCIE_USE_MODE">2.0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PER_FUNC_STATUS_IF">TRUE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_AER_CAP_ECRC_CHECK_CAPABLE">FALSE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_AER_CAP_ECRC_GEN_CAPABLE">FALSE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_AER_CAP_NEXTPTR">0x300</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_ARI_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_ARI_CAP_NEXT_FUNC">0x00</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR0_APERTURE_SIZE">0x11</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR0_CONTROL">0x4</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR1_APERTURE_SIZE">0x11</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR1_CONTROL">0x4</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR2_APERTURE_SIZE">0x00</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR2_CONTROL">0x0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR3_APERTURE_SIZE">0x00</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR3_CONTROL">0x0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR4_APERTURE_SIZE">0x00</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR4_CONTROL">0x0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR5_APERTURE_SIZE">0x00</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR5_CONTROL">0x0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_CAPABILITY_POINTER">0x80</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_CLASS_CODE">0x020000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEVICE_ID">0x0001</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT">FALSE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT">FALSE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT">FALSE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP2_LTR_SUPPORT">FALSE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP2_OBFF_SUPPORT">0x0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT">FALSE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP_EXT_TAG_SUPPORTED">TRUE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE">FALSE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP_MAX_PAYLOAD_SIZE">0x2</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DPA_CAP_NEXTPTR">0x300</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0">0x00</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1">0x00</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2">0x00</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3">0x00</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4">0x00</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5">0x00</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6">0x00</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7">0x00</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DSN_CAP_NEXTPTR">0x300</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_EXPANSION_ROM_APERTURE_SIZE">0x00</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_EXPANSION_ROM_ENABLE">FALSE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_INTERRUPT_PIN">0x1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_LINK_CAP_ASPM_SUPPORT">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_LINK_STATUS_SLOT_CLOCK_CONFIG">TRUE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_LTR_CAP_NEXTPTR">0x300</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_MSIX_CAP_NEXTPTR">0x00</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_MSIX_CAP_PBA_BIR">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_MSIX_CAP_PBA_OFFSET">0x00000000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_MSIX_CAP_TABLE_BIR">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_MSIX_CAP_TABLE_OFFSET">0x00000000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_MSIX_CAP_TABLE_SIZE">0x000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_MSI_CAP_MULTIMSGCAP">5</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_MSI_CAP_NEXTPTR">0xC0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_PB_CAP_NEXTPTR">0x274</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_PM_CAP_NEXTPTR">0x90</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_PM_CAP_PMESUPPORT_D0">FALSE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_PM_CAP_PMESUPPORT_D1">FALSE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_PM_CAP_PMESUPPORT_D3HOT">FALSE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_PM_CAP_SUPP_D1_STATE">FALSE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_RBAR_CAP_ENABLE">FALSE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_RBAR_CAP_NEXTPTR">0x300</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_RBAR_CAP_SIZE0">0x00000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_RBAR_CAP_SIZE1">0x00000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_RBAR_CAP_SIZE2">0x00000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_REVISION_ID">0x00</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SECONDARY_PCIE_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR0_APERTURE_SIZE">0x00</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR0_CONTROL">0x0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR1_APERTURE_SIZE">0x00</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR1_CONTROL">0x0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR2_APERTURE_SIZE">0x00</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR2_CONTROL">0x0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR3_APERTURE_SIZE">0x00</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR3_CONTROL">0x0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR4_APERTURE_SIZE">0x00</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR4_CONTROL">0x0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR5_APERTURE_SIZE">0x00</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR5_CONTROL">0x0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_CAP_INITIAL_VF">0x0000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_CAP_NEXTPTR">0x300</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_CAP_TOTAL_VF">0x0000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_CAP_VER">0x0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_FIRST_VF_OFFSET">0x0000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_FUNC_DEP_LINK">0x0000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_SUPPORTED_PAGE_SIZE">0x00000553</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_VF_DEVICE_ID">0x0000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SUBSYSTEM_ID">0x0001</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SUBSYSTEM_VENDOR_ID">0x1234</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_TPHR_CAP_DEV_SPECIFIC_MODE">TRUE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_TPHR_CAP_ENABLE">FALSE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_TPHR_CAP_INT_VEC_MODE">FALSE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_TPHR_CAP_NEXTPTR">0x300</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_TPHR_CAP_ST_MODE_SEL">0x0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_TPHR_CAP_ST_TABLE_LOC">0x0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_TPHR_CAP_ST_TABLE_SIZE">0x000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_TPHR_CAP_VER">0x1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_VC_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_VENDOR_ID">0x1234</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_AER_CAP_ECRC_CHECK_CAPABLE">FALSE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_AER_CAP_ECRC_GEN_CAPABLE">FALSE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_AER_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_ARI_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR0_APERTURE_SIZE">0x00</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR0_CONTROL">0x0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR1_APERTURE_SIZE">0x00</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR1_CONTROL">0x0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR2_APERTURE_SIZE">0x00</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR2_CONTROL">0x0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR3_APERTURE_SIZE">0x00</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR3_CONTROL">0x0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR4_APERTURE_SIZE">0x00</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR4_CONTROL">0x0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR5_APERTURE_SIZE">0x00</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR5_CONTROL">0x0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_CAPABILITY_POINTER">0x80</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_CLASS_CODE">0x058000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DEVICE_ID">0x8011</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DEV_CAP_MAX_PAYLOAD_SIZE">0x2</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DPA_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0">0x00</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1">0x00</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2">0x00</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3">0x00</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4">0x00</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5">0x00</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6">0x00</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7">0x00</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DSN_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_EXPANSION_ROM_APERTURE_SIZE">0x00</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_EXPANSION_ROM_ENABLE">FALSE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_INTERRUPT_PIN">0x0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_MSIX_CAP_NEXTPTR">0x00</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_MSIX_CAP_PBA_BIR">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_MSIX_CAP_PBA_OFFSET">0x00000000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_MSIX_CAP_TABLE_BIR">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_MSIX_CAP_TABLE_OFFSET">0x00000000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_MSIX_CAP_TABLE_SIZE">0x000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_MSI_CAP_MULTIMSGCAP">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_MSI_CAP_NEXTPTR">0x00</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_PB_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_PM_CAP_NEXTPTR">0x00</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_RBAR_CAP_ENABLE">FALSE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_RBAR_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_RBAR_CAP_SIZE0">0x00000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_RBAR_CAP_SIZE1">0x00000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_RBAR_CAP_SIZE2">0x00000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_REVISION_ID">0x00</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_BAR0_APERTURE_SIZE">0x00</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_BAR0_CONTROL">0x0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_BAR1_APERTURE_SIZE">0x00</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_BAR1_CONTROL">0x0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_BAR2_APERTURE_SIZE">0x00</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_BAR2_CONTROL">0x0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_BAR3_APERTURE_SIZE">0x00</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_BAR3_CONTROL">0x0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_BAR4_APERTURE_SIZE">0x00</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_BAR4_CONTROL">0x0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_BAR5_APERTURE_SIZE">0x00</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_BAR5_CONTROL">0x0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_CAP_INITIAL_VF">0x0000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_CAP_TOTAL_VF">0x0000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_CAP_VER">0x0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_FIRST_VF_OFFSET">0x0000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_FUNC_DEP_LINK">0x0001</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_SUPPORTED_PAGE_SIZE">0x00000553</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SRIOV_VF_DEVICE_ID">0x0000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SUBSYSTEM_ID">0x0007</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_TPHR_CAP_DEV_SPECIFIC_MODE">TRUE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_TPHR_CAP_ENABLE">FALSE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_TPHR_CAP_INT_VEC_MODE">FALSE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_TPHR_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_TPHR_CAP_ST_MODE_SEL">0x0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_TPHR_CAP_ST_TABLE_LOC">0x0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_TPHR_CAP_ST_TABLE_SIZE">0x000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_TPHR_CAP_VER">0x1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PHY_LP_TXPRESET">4</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PIPE_SIM">FALSE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PLL_TYPE">2</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PL_INTERFACE">FALSE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_SPEED">4</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH">8</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PL_UPSTREAM_FACING">TRUE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PM_ENABLE_L23_ENTRY">FALSE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RCV_MSG_IF">TRUE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.REF_CLK_FREQ">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RX_DETECT">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SELECT_QUAD">GTH_Quad_225</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SHARED_LOGIC">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SPARE_WORD1">0x00000000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SRIOV_CAP_ENABLE">FALSE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SYS_RESET_POLARITY">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TL_CREDITS_CD">0x000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TL_CREDITS_CH">0x00</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TL_CREDITS_NPD">0x028</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TL_CREDITS_NPH">0x20</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TL_CREDITS_PD">0x198</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TL_CREDITS_PH">0x20</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE">FALSE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TL_LEGACY_MODE_ENABLE">FALSE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TL_PF_ENABLE_REG">0x0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TRANSCEIVER_CTRL_STATUS_PORTS">FALSE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TX_FC_IF">TRUE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.USER_CLK_FREQ">3</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_ARI_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_CAPABILITY_POINTER">0x80</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_MSIX_CAP_PBA_BIR">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_MSIX_CAP_PBA_OFFSET">0x00000000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_MSIX_CAP_TABLE_BIR">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_MSIX_CAP_TABLE_OFFSET">0x00000000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_MSIX_CAP_TABLE_SIZE">0x000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_MSI_CAP_MULTIMSGCAP">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_PM_CAP_NEXTPTR">0x00</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_TPHR_CAP_DEV_SPECIFIC_MODE">TRUE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_TPHR_CAP_INT_VEC_MODE">FALSE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_TPHR_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_TPHR_CAP_ST_MODE_SEL">0x0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_TPHR_CAP_ST_TABLE_LOC">0x0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_TPHR_CAP_ST_TABLE_SIZE">0x000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_TPHR_CAP_VER">0x1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_ARI_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_MSIX_CAP_PBA_BIR">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_MSIX_CAP_PBA_OFFSET">0x00000000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_MSIX_CAP_TABLE_BIR">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_MSIX_CAP_TABLE_OFFSET">0x00000000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_MSIX_CAP_TABLE_SIZE">0x000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_MSI_CAP_MULTIMSGCAP">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_PM_CAP_NEXTPTR">0x00</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_TPHR_CAP_DEV_SPECIFIC_MODE">TRUE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_TPHR_CAP_INT_VEC_MODE">FALSE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_TPHR_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_TPHR_CAP_ST_MODE_SEL">0x0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_TPHR_CAP_ST_TABLE_LOC">0x0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_TPHR_CAP_ST_TABLE_SIZE">0x000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF1_TPHR_CAP_VER">0x1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_ARI_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_MSIX_CAP_PBA_BIR">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_MSIX_CAP_PBA_OFFSET">0x00000000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_MSIX_CAP_TABLE_BIR">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_MSIX_CAP_TABLE_OFFSET">0x00000000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_MSIX_CAP_TABLE_SIZE">0x000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_MSI_CAP_MULTIMSGCAP">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_PM_CAP_NEXTPTR">0x00</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_TPHR_CAP_DEV_SPECIFIC_MODE">TRUE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_TPHR_CAP_INT_VEC_MODE">FALSE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_TPHR_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_TPHR_CAP_ST_MODE_SEL">0x0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_TPHR_CAP_ST_TABLE_LOC">0x0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_TPHR_CAP_ST_TABLE_SIZE">0x000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF2_TPHR_CAP_VER">0x1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF3_ARI_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF3_MSIX_CAP_PBA_BIR">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF3_MSIX_CAP_PBA_OFFSET">0x00000000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF3_MSIX_CAP_TABLE_BIR">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF3_MSIX_CAP_TABLE_OFFSET">0x00000000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF3_MSIX_CAP_TABLE_SIZE">0x000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF3_MSI_CAP_MULTIMSGCAP">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF3_PM_CAP_NEXTPTR">0x00</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF3_TPHR_CAP_DEV_SPECIFIC_MODE">TRUE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF3_TPHR_CAP_INT_VEC_MODE">FALSE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF3_TPHR_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF3_TPHR_CAP_ST_MODE_SEL">0x0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF3_TPHR_CAP_ST_TABLE_LOC">0x0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF3_TPHR_CAP_ST_TABLE_SIZE">0x000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF3_TPHR_CAP_VER">0x1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF4_ARI_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF4_MSIX_CAP_PBA_BIR">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF4_MSIX_CAP_PBA_OFFSET">0x00000000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF4_MSIX_CAP_TABLE_BIR">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF4_MSIX_CAP_TABLE_OFFSET">0x00000000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF4_MSIX_CAP_TABLE_SIZE">0x000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF4_MSI_CAP_MULTIMSGCAP">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF4_PM_CAP_NEXTPTR">0x00</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF4_TPHR_CAP_DEV_SPECIFIC_MODE">TRUE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF4_TPHR_CAP_INT_VEC_MODE">FALSE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF4_TPHR_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF4_TPHR_CAP_ST_MODE_SEL">0x0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF4_TPHR_CAP_ST_TABLE_LOC">0x0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF4_TPHR_CAP_ST_TABLE_SIZE">0x000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF4_TPHR_CAP_VER">0x1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF5_ARI_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF5_MSIX_CAP_PBA_BIR">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF5_MSIX_CAP_PBA_OFFSET">0x00000000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF5_MSIX_CAP_TABLE_BIR">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF5_MSIX_CAP_TABLE_OFFSET">0x00000000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF5_MSIX_CAP_TABLE_SIZE">0x000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF5_MSI_CAP_MULTIMSGCAP">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF5_PM_CAP_NEXTPTR">0x00</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF5_TPHR_CAP_DEV_SPECIFIC_MODE">TRUE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF5_TPHR_CAP_INT_VEC_MODE">FALSE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF5_TPHR_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF5_TPHR_CAP_ST_MODE_SEL">0x0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF5_TPHR_CAP_ST_TABLE_LOC">0x0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF5_TPHR_CAP_ST_TABLE_SIZE">0x000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF5_TPHR_CAP_VER">0x1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.en_msi_per_vec_masking">FALSE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gen_x0y0_xdc">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gen_x0y1_xdc">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gen_x0y2_xdc">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gen_x0y3_xdc">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gen_x0y4_xdc">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gen_x0y5_xdc">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.pcie_blk_locn">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.silicon_revision">Production</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.xlnx_ref_board">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.xlnx_ref_board">true</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXISTEN_IF_RC_STRADDLE">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">pcie3_ultrascale_0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INS_LOSS_NYQ">15</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_AER_CAP_ECRC_CHECK_CAPABLE">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_AER_CAP_ECRC_GEN_CAPABLE">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_CLASS_CODE">020000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_DEVICE_ID">0001</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_DEV_CAP2_OBFF_SUPPORT">00_Not_Supported</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_INTERRUPT_PIN">INTA</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_LINK_STATUS_SLOT_CLOCK_CONFIG">true</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_MSIX_CAP_TABLE_SIZE">000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_MSI_CAP_MULTIMSGCAP">32_vectors</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_PM_CAP_PMESUPPORT_D0">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_PM_CAP_PMESUPPORT_D1">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_PM_CAP_PMESUPPORT_D3HOT">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_PM_CAP_SUPP_D1_STATE">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_REVISION_ID">00</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SRIOV_CAP_INITIAL_VF">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SRIOV_FIRST_VF_OFFSET">N/A</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SRIOV_FUNC_DEP_LINK">0000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SRIOV_SUPPORTED_PAGE_SIZE">00000553</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SRIOV_VF_DEVICE_ID">0000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SUBSYSTEM_ID">0001</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SUBSYSTEM_VENDOR_ID">1234</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_Use_Class_Code_Lookup_Assistant">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_AER_CAP_ECRC_CHECK_CAPABLE">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_AER_CAP_ECRC_GEN_CAPABLE">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_CLASS_CODE">058000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_DEVICE_ID">8011</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_INTERRUPT_PIN">NONE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_MSIX_CAP_TABLE_SIZE">000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_MSI_CAP_MULTIMSGCAP">1_vector</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_REVISION_ID">00</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SRIOV_CAP_INITIAL_VF">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SRIOV_CAP_VER">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SRIOV_FIRST_VF_OFFSET">N/A</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SRIOV_FUNC_DEP_LINK">0001</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SRIOV_SUPPORTED_PAGE_SIZE">00000553</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SRIOV_VF_DEVICE_ID">0000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SUBSYSTEM_ID">0007</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_Use_Class_Code_Lookup_Assistant">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHY_LP_TXPRESET">4</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PL_LINK_CAP_MAX_LINK_SPEED">8.0_GT/s</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH">X8</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REF_CLK_FREQ">100_MHz</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RX_DETECT">Default</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RX_PPM_OFFSET">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RX_SSC_PPM">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SRIOV_CAP_ENABLE">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SRIOV_CAP_ENABLE_EXT">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Shared_Logic">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TL_PF_ENABLE_REG">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF0_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF0_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF0_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF0_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF0_MSIX_CAP_TABLE_SIZE">000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF0_MSI_CAP_MULTIMSGCAP">1_vector</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF1_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF1_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF1_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF1_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF1_MSIX_CAP_TABLE_SIZE">000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF1_MSI_CAP_MULTIMSGCAP">1_vector</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF2_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF2_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF2_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF2_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF2_MSIX_CAP_TABLE_SIZE">000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF2_MSI_CAP_MULTIMSGCAP">1_vector</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF3_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF3_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF3_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF3_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF3_MSIX_CAP_TABLE_SIZE">000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF3_MSI_CAP_MULTIMSGCAP">1_vector</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF4_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF4_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF4_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF4_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF4_MSIX_CAP_TABLE_SIZE">000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF4_MSI_CAP_MULTIMSGCAP">1_vector</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF5_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF5_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF5_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF5_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF5_MSIX_CAP_TABLE_SIZE">000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VF5_MSI_CAP_MULTIMSGCAP">1_vector</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.acs_ext_cap_enable">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.alignment_mode">DWORD_Aligned</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.aspm_support">No_ASPM</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axisten_freq">250</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axisten_if_enable_client_tag">true</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axisten_if_enable_msg_route">2FFFF</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axisten_if_enable_msg_route_override">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axisten_if_enable_rx_msg_intfc">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axisten_if_width">256_bit</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.bmd_pio_mode">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cc_cq_alignment">None</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_ctl_if">true</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_ext_if">true</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_fc_if">true</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_mgmt_if">true</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_status_if">true</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_tx_msg_if">true</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.coreclk_freq">500</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dedicate_perst">true</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.device_port_type">PCI_Express_Endpoint_device</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dis_gt_wizard">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.disable_gt_loc">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_dbg_descramble">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_ext_ch_gt_drp">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_ext_clk">true</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_gt_selection">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_l23_entry">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_msi_per_vec_masking">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_parity">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_pcie_conf">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_pcie_drp">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_pl_ifc">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_transceiver_status_ports">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_auto_rxeq">False</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_gt_v1_5">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_ibert">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_jtag_dbg">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ext_pcie_cfg_space_enabled">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ext_startup_primitive">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ext_xvc_vsec_enable">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.extended_tag_field">true</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.free_run_freq">100_MHz</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gen_x0y0">true</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gen_x0y1">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gen_x0y2">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gen_x0y3">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gen_x0y4">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gen_x0y5">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_drp_clk_src">Internal</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtwiz_in_core">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ins_loss_profile">Add-in_Card</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.mcap_enablement">None</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.mcap_fpga_bitstream_version">00000000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.mode_selection">Basic</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.mult_pf_des">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_blk_locn">X0Y0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.per_func_status_if">true</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.perf_level">Extreme</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.performance">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_aer_enabled">true</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_ari_enabled">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_64bit">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_enabled">true</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_prefetchable">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_scale">Megabytes</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_size">16</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_type">Memory</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_64bit">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_enabled">true</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_prefetchable">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_scale">Megabytes</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_size">16</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_type">Memory</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_64bit">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_enabled">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_prefetchable">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_scale">Kilobytes</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_size">2</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_type">N/A</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_64bit">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_enabled">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_prefetchable">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_scale">Kilobytes</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_size">2</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_type">N/A</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_64bit">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_enabled">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_prefetchable">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_scale">Kilobytes</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_size">2</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_type">N/A</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_enabled">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_prefetchable">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_scale">Kilobytes</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_size">2</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_type">N/A</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_base_class_menu">Network_controller</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_class_code_base">02</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_class_code_interface">00</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_class_code_sub">00</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_dev_cap_max_payload">512_bytes</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_dpa_enabled">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_dsn_enabled">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_expansion_rom_enabled">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_expansion_rom_scale">Kilobytes</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_expansion_rom_size">2</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_ltr_enabled">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_msi_enabled">true</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_msix_enabled">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_pb_enabled">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_rbar_enabled">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_64bit">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_enabled">true</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_prefetchable">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_scale">Kilobytes</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_size">2</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_type">Memory</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_64bit">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_enabled">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_prefetchable">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_scale">Kilobytes</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_size">2</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_type">N/A</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar2_64bit">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar2_enabled">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar2_prefetchable">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar2_scale">Kilobytes</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar2_size">2</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar2_type">N/A</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar3_64bit">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar3_enabled">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar3_prefetchable">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar3_scale">Kilobytes</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar3_size">2</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar3_type">N/A</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar4_64bit">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar4_enabled">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar4_prefetchable">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar4_scale">Kilobytes</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar4_size">2</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar4_type">N/A</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar5_enabled">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar5_prefetchable">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar5_scale">Kilobytes</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar5_size">2</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar5_type">N/A</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_cap_ver">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sub_class_interface_menu">Ethernet_controller</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_tphr_enable">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_vc_cap_enabled">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_aer_enabled">true</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_ari_enabled">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_64bit">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_enabled">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_prefetchable">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_scale">Kilobytes</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_size">2</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_type">N/A</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_64bit">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_enabled">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_prefetchable">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_scale">Kilobytes</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_size">2</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_type">N/A</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_64bit">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_enabled">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_prefetchable">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_scale">Kilobytes</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_size">2</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_type">N/A</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_64bit">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_enabled">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_prefetchable">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_scale">Kilobytes</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_size">2</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_type">N/A</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_64bit">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_enabled">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_prefetchable">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_scale">Kilobytes</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_size">2</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_type">N/A</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_enabled">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_prefetchable">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_scale">Kilobytes</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_size">2</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_type">N/A</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_base_class_menu">Memory_controller</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_class_code_base">05</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_class_code_interface">00</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_class_code_sub">80</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_dev_cap_max_payload">512_bytes</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_dpa_enabled">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_dsn_enabled">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_expansion_rom_enabled">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_expansion_rom_scale">Kilobytes</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_expansion_rom_size">2</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_msi_enabled">true</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_msix_enabled">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_pb_enabled">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_rbar_enabled">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar0_64bit">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar0_enabled">true</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar0_prefetchable">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar0_scale">Kilobytes</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar0_size">2</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar0_type">Memory</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar1_64bit">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar1_enabled">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar1_prefetchable">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar1_scale">Kilobytes</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar1_size">2</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar1_type">N/A</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar2_64bit">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar2_enabled">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar2_prefetchable">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar2_scale">Kilobytes</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar2_size">2</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar2_type">N/A</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_64bit">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_enabled">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_prefetchable">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_scale">Kilobytes</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_size">2</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_type">N/A</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar4_64bit">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar4_enabled">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar4_prefetchable">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar4_scale">Kilobytes</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar4_size">2</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar4_type">N/A</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar5_enabled">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar5_prefetchable">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar5_scale">Kilobytes</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar5_size">2</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar5_type">N/A</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sub_class_interface_menu">Other_memory_controller</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_tphr_enable">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pipe_sim">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.plltype">QPLL1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rc_rq_alignment">None</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rcv_msg_if">true</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.select_quad">GTH_Quad_225</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.special_gui">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.sys_reset_polarity">ACTIVE_LOW</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.tandem_mode">None</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.tl_pf0_enable_reg">true</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.tx_fc_if">true</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.vendor_id">1234</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.xlnx_ref_board">None</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintexu</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xcku035</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fbva676</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">E</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">5</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
|
||||||
|
</spirit:configurableElementValues>
|
||||||
|
<spirit:vendorExtensions>
|
||||||
|
<xilinx:componentInstanceExtensions>
|
||||||
|
<xilinx:configElementInfos>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.HAS_TKEEP" xilinx:valueSource="auto"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.HAS_TLAST" xilinx:valueSource="constant"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.HAS_TREADY" xilinx:valueSource="constant"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.HAS_TSTRB" xilinx:valueSource="constant"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.TDEST_WIDTH" xilinx:valueSource="constant"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.TID_WIDTH" xilinx:valueSource="constant"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.TUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.HAS_TKEEP" xilinx:valueSource="auto"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.HAS_TLAST" xilinx:valueSource="constant"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.HAS_TREADY" xilinx:valueSource="constant"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.HAS_TSTRB" xilinx:valueSource="constant"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.TDEST_WIDTH" xilinx:valueSource="constant"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.TID_WIDTH" xilinx:valueSource="constant"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.TUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.HAS_TKEEP" xilinx:valueSource="auto"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.HAS_TLAST" xilinx:valueSource="constant"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.HAS_TREADY" xilinx:valueSource="constant"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.HAS_TSTRB" xilinx:valueSource="constant"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.TDEST_WIDTH" xilinx:valueSource="constant"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.TID_WIDTH" xilinx:valueSource="constant"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.TUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.HAS_TKEEP" xilinx:valueSource="auto"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.HAS_TLAST" xilinx:valueSource="constant"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.HAS_TREADY" xilinx:valueSource="constant"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.HAS_TSTRB" xilinx:valueSource="constant"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.TDEST_WIDTH" xilinx:valueSource="constant"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.TID_WIDTH" xilinx:valueSource="constant"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.TUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.AXISTEN_IF_RC_STRADDLE" xilinx:valueSource="user"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PF0_CLASS_CODE" xilinx:valueSource="user"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PF0_DEVICE_ID" xilinx:valueSource="user"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PF0_MSIX_CAP_PBA_BIR" xilinx:valueSource="user"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PF0_MSIX_CAP_TABLE_BIR" xilinx:valueSource="user"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PF0_MSI_CAP_MULTIMSGCAP" xilinx:valueSource="user"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PF0_SRIOV_CAP_INITIAL_VF" xilinx:valueSource="user"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PF0_SUBSYSTEM_ID" xilinx:valueSource="user"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PF0_SUBSYSTEM_VENDOR_ID" xilinx:valueSource="user"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PF0_Use_Class_Code_Lookup_Assistant" xilinx:valueSource="user"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PF1_DEVICE_ID" xilinx:valueSource="user"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PF1_MSIX_CAP_PBA_BIR" xilinx:valueSource="user"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PF1_MSIX_CAP_TABLE_BIR" xilinx:valueSource="user"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PF1_SRIOV_CAP_INITIAL_VF" xilinx:valueSource="user"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PL_LINK_CAP_MAX_LINK_SPEED" xilinx:valueSource="user"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH" xilinx:valueSource="user"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TL_PF_ENABLE_REG" xilinx:valueSource="user"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.aspm_support" xilinx:valueSource="user"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.axisten_freq" xilinx:valueSource="user"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.axisten_if_width" xilinx:valueSource="user"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.coreclk_freq" xilinx:valueSource="user"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.dedicate_perst" xilinx:valueSource="user"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.extended_tag_field" xilinx:valueSource="user"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gen_x0y0" xilinx:valueSource="user"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gen_x0y1" xilinx:valueSource="user"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.mcap_enablement" xilinx:valueSource="user"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.mult_pf_des" xilinx:valueSource="user"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pcie_blk_locn" xilinx:valueSource="user"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_bar0_64bit" xilinx:valueSource="user"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_bar0_scale" xilinx:valueSource="user"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_bar0_size" xilinx:valueSource="user"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_bar1_enabled" xilinx:valueSource="user"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_bar1_scale" xilinx:valueSource="user"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_bar1_size" xilinx:valueSource="user"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_bar1_type" xilinx:valueSource="user"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_base_class_menu" xilinx:valueSource="user"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_class_code_base" xilinx:valueSource="user"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_class_code_interface" xilinx:valueSource="user"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_class_code_sub" xilinx:valueSource="user"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_sub_class_interface_menu" xilinx:valueSource="user"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf1_bar0_enabled" xilinx:valueSource="user"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf1_bar0_size" xilinx:valueSource="user"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf1_bar0_type" xilinx:valueSource="user"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pipe_sim" xilinx:valueSource="user"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.plltype" xilinx:valueSource="user"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.select_quad" xilinx:valueSource="user"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.vendor_id" xilinx:valueSource="user"/>
|
||||||
|
</xilinx:configElementInfos>
|
||||||
|
</xilinx:componentInstanceExtensions>
|
||||||
|
</spirit:vendorExtensions>
|
||||||
|
</spirit:componentInstance>
|
||||||
|
</spirit:componentInstances>
|
||||||
|
</spirit:design>
|
||||||
1
example/ExaNIC_X10/fpga/lib/pcie
Symbolic link
1
example/ExaNIC_X10/fpga/lib/pcie
Symbolic link
@ -0,0 +1 @@
|
|||||||
|
../../../../
|
||||||
365
example/ExaNIC_X10/fpga/rtl/axi_ram.v
Normal file
365
example/ExaNIC_X10/fpga/rtl/axi_ram.v
Normal file
@ -0,0 +1,365 @@
|
|||||||
|
/*
|
||||||
|
|
||||||
|
Copyright (c) 2018 Alex Forencich
|
||||||
|
|
||||||
|
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||||
|
of this software and associated documentation files (the "Software"), to deal
|
||||||
|
in the Software without restriction, including without limitation the rights
|
||||||
|
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||||
|
copies of the Software, and to permit persons to whom the Software is
|
||||||
|
furnished to do so, subject to the following conditions:
|
||||||
|
|
||||||
|
The above copyright notice and this permission notice shall be included in
|
||||||
|
all copies or substantial portions of the Software.
|
||||||
|
|
||||||
|
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||||
|
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||||
|
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||||
|
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||||
|
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||||
|
THE SOFTWARE.
|
||||||
|
|
||||||
|
*/
|
||||||
|
|
||||||
|
// Language: Verilog 2001
|
||||||
|
|
||||||
|
`timescale 1ns / 1ps
|
||||||
|
|
||||||
|
/*
|
||||||
|
* AXI4 RAM
|
||||||
|
*/
|
||||||
|
module axi_ram #
|
||||||
|
(
|
||||||
|
parameter DATA_WIDTH = 32, // width of data bus in bits
|
||||||
|
parameter ADDR_WIDTH = 16, // width of address bus in bits
|
||||||
|
parameter STRB_WIDTH = (DATA_WIDTH/8),
|
||||||
|
parameter ID_WIDTH = 8,
|
||||||
|
parameter PIPELINE_OUTPUT = 0
|
||||||
|
)
|
||||||
|
(
|
||||||
|
input wire clk,
|
||||||
|
input wire rst,
|
||||||
|
|
||||||
|
input wire [ID_WIDTH-1:0] s_axi_awid,
|
||||||
|
input wire [ADDR_WIDTH-1:0] s_axi_awaddr,
|
||||||
|
input wire [7:0] s_axi_awlen,
|
||||||
|
input wire [2:0] s_axi_awsize,
|
||||||
|
input wire [1:0] s_axi_awburst,
|
||||||
|
input wire s_axi_awlock,
|
||||||
|
input wire [3:0] s_axi_awcache,
|
||||||
|
input wire [2:0] s_axi_awprot,
|
||||||
|
input wire s_axi_awvalid,
|
||||||
|
output wire s_axi_awready,
|
||||||
|
input wire [DATA_WIDTH-1:0] s_axi_wdata,
|
||||||
|
input wire [STRB_WIDTH-1:0] s_axi_wstrb,
|
||||||
|
input wire s_axi_wlast,
|
||||||
|
input wire s_axi_wvalid,
|
||||||
|
output wire s_axi_wready,
|
||||||
|
output wire [ID_WIDTH-1:0] s_axi_bid,
|
||||||
|
output wire [1:0] s_axi_bresp,
|
||||||
|
output wire s_axi_bvalid,
|
||||||
|
input wire s_axi_bready,
|
||||||
|
input wire [ID_WIDTH-1:0] s_axi_arid,
|
||||||
|
input wire [ADDR_WIDTH-1:0] s_axi_araddr,
|
||||||
|
input wire [7:0] s_axi_arlen,
|
||||||
|
input wire [2:0] s_axi_arsize,
|
||||||
|
input wire [1:0] s_axi_arburst,
|
||||||
|
input wire s_axi_arlock,
|
||||||
|
input wire [3:0] s_axi_arcache,
|
||||||
|
input wire [2:0] s_axi_arprot,
|
||||||
|
input wire s_axi_arvalid,
|
||||||
|
output wire s_axi_arready,
|
||||||
|
output wire [ID_WIDTH-1:0] s_axi_rid,
|
||||||
|
output wire [DATA_WIDTH-1:0] s_axi_rdata,
|
||||||
|
output wire [1:0] s_axi_rresp,
|
||||||
|
output wire s_axi_rlast,
|
||||||
|
output wire s_axi_rvalid,
|
||||||
|
input wire s_axi_rready
|
||||||
|
);
|
||||||
|
|
||||||
|
parameter VALID_ADDR_WIDTH = ADDR_WIDTH - $clog2(STRB_WIDTH);
|
||||||
|
parameter WORD_WIDTH = STRB_WIDTH;
|
||||||
|
parameter WORD_SIZE = DATA_WIDTH/WORD_WIDTH;
|
||||||
|
|
||||||
|
// bus width assertions
|
||||||
|
initial begin
|
||||||
|
if (WORD_SIZE * STRB_WIDTH != DATA_WIDTH) begin
|
||||||
|
$error("Error: AXI data width not evenly divisble");
|
||||||
|
$finish;
|
||||||
|
end
|
||||||
|
|
||||||
|
if (2**$clog2(WORD_WIDTH) != WORD_WIDTH) begin
|
||||||
|
$error("Error: AXI word width must be even power of two");
|
||||||
|
$finish;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
localparam [0:0]
|
||||||
|
READ_STATE_IDLE = 1'd0,
|
||||||
|
READ_STATE_BURST = 1'd1;
|
||||||
|
|
||||||
|
reg [0:0] read_state_reg = READ_STATE_IDLE, read_state_next;
|
||||||
|
|
||||||
|
localparam [1:0]
|
||||||
|
WRITE_STATE_IDLE = 2'd0,
|
||||||
|
WRITE_STATE_BURST = 2'd1,
|
||||||
|
WRITE_STATE_RESP = 2'd2;
|
||||||
|
|
||||||
|
reg [1:0] write_state_reg = WRITE_STATE_IDLE, write_state_next;
|
||||||
|
|
||||||
|
reg mem_wr_en;
|
||||||
|
reg mem_rd_en;
|
||||||
|
|
||||||
|
reg [ID_WIDTH-1:0] read_id_reg = {ID_WIDTH{1'b0}}, read_id_next;
|
||||||
|
reg [ADDR_WIDTH-1:0] read_addr_reg = {ADDR_WIDTH{1'b0}}, read_addr_next;
|
||||||
|
reg [7:0] read_count_reg = 8'd0, read_count_next;
|
||||||
|
reg [2:0] read_size_reg = 3'd0, read_size_next;
|
||||||
|
reg [1:0] read_burst_reg = 2'd0, read_burst_next;
|
||||||
|
reg [ID_WIDTH-1:0] write_id_reg = {ID_WIDTH{1'b0}}, write_id_next;
|
||||||
|
reg [ADDR_WIDTH-1:0] write_addr_reg = {ADDR_WIDTH{1'b0}}, write_addr_next;
|
||||||
|
reg [7:0] write_count_reg = 8'd0, write_count_next;
|
||||||
|
reg [2:0] write_size_reg = 3'd0, write_size_next;
|
||||||
|
reg [1:0] write_burst_reg = 2'd0, write_burst_next;
|
||||||
|
|
||||||
|
reg s_axi_awready_reg = 1'b0, s_axi_awready_next;
|
||||||
|
reg s_axi_wready_reg = 1'b0, s_axi_wready_next;
|
||||||
|
reg [ID_WIDTH-1:0] s_axi_bid_reg = {ID_WIDTH{1'b0}}, s_axi_bid_next;
|
||||||
|
reg s_axi_bvalid_reg = 1'b0, s_axi_bvalid_next;
|
||||||
|
reg s_axi_arready_reg = 1'b0, s_axi_arready_next;
|
||||||
|
reg [ID_WIDTH-1:0] s_axi_rid_reg = {ID_WIDTH{1'b0}}, s_axi_rid_next;
|
||||||
|
reg [DATA_WIDTH-1:0] s_axi_rdata_reg = {DATA_WIDTH{1'b0}}, s_axi_rdata_next;
|
||||||
|
reg s_axi_rlast_reg = 1'b0, s_axi_rlast_next;
|
||||||
|
reg s_axi_rvalid_reg = 1'b0, s_axi_rvalid_next;
|
||||||
|
reg [ID_WIDTH-1:0] s_axi_rid_pipe_reg = {ID_WIDTH{1'b0}};
|
||||||
|
reg [DATA_WIDTH-1:0] s_axi_rdata_pipe_reg = {DATA_WIDTH{1'b0}};
|
||||||
|
reg s_axi_rlast_pipe_reg = 1'b0;
|
||||||
|
reg s_axi_rvalid_pipe_reg = 1'b0;
|
||||||
|
|
||||||
|
// (* RAM_STYLE="BLOCK" *)
|
||||||
|
reg [DATA_WIDTH-1:0] mem[(2**VALID_ADDR_WIDTH)-1:0];
|
||||||
|
|
||||||
|
wire [VALID_ADDR_WIDTH-1:0] s_axi_awaddr_valid = s_axi_awaddr >> (ADDR_WIDTH - VALID_ADDR_WIDTH);
|
||||||
|
wire [VALID_ADDR_WIDTH-1:0] s_axi_araddr_valid = s_axi_araddr >> (ADDR_WIDTH - VALID_ADDR_WIDTH);
|
||||||
|
wire [VALID_ADDR_WIDTH-1:0] read_addr_valid = read_addr_reg >> (ADDR_WIDTH - VALID_ADDR_WIDTH);
|
||||||
|
wire [VALID_ADDR_WIDTH-1:0] write_addr_valid = write_addr_reg >> (ADDR_WIDTH - VALID_ADDR_WIDTH);
|
||||||
|
|
||||||
|
assign s_axi_awready = s_axi_awready_reg;
|
||||||
|
assign s_axi_wready = s_axi_wready_reg;
|
||||||
|
assign s_axi_bid = s_axi_bid_reg;
|
||||||
|
assign s_axi_bresp = 2'b00;
|
||||||
|
assign s_axi_bvalid = s_axi_bvalid_reg;
|
||||||
|
assign s_axi_arready = s_axi_arready_reg;
|
||||||
|
assign s_axi_rid = PIPELINE_OUTPUT ? s_axi_rid_pipe_reg : s_axi_rid_reg;
|
||||||
|
assign s_axi_rdata = PIPELINE_OUTPUT ? s_axi_rdata_pipe_reg : s_axi_rdata_reg;
|
||||||
|
assign s_axi_rresp = 2'b00;
|
||||||
|
assign s_axi_rlast = PIPELINE_OUTPUT ? s_axi_rlast_pipe_reg : s_axi_rlast_reg;
|
||||||
|
assign s_axi_rvalid = PIPELINE_OUTPUT ? s_axi_rvalid_pipe_reg : s_axi_rvalid_reg;
|
||||||
|
|
||||||
|
integer i, j;
|
||||||
|
|
||||||
|
initial begin
|
||||||
|
// two nested loops for smaller number of iterations per loop
|
||||||
|
// workaround for synthesizer complaints about large loop counts
|
||||||
|
for (i = 0; i < 2**ADDR_WIDTH; i = i + 2**(ADDR_WIDTH/2)) begin
|
||||||
|
for (j = i; j < i + 2**(ADDR_WIDTH/2); j = j + 1) begin
|
||||||
|
mem[j] = 0;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
always @* begin
|
||||||
|
write_state_next = WRITE_STATE_IDLE;
|
||||||
|
|
||||||
|
mem_wr_en = 1'b0;
|
||||||
|
|
||||||
|
write_id_next = write_id_reg;
|
||||||
|
write_addr_next = write_addr_reg;
|
||||||
|
write_count_next = write_count_reg;
|
||||||
|
write_size_next = write_size_reg;
|
||||||
|
write_burst_next = write_burst_reg;
|
||||||
|
|
||||||
|
s_axi_awready_next = 1'b0;
|
||||||
|
s_axi_wready_next = 1'b0;
|
||||||
|
s_axi_bid_next = s_axi_bid_reg;
|
||||||
|
s_axi_bvalid_next = s_axi_bvalid_reg && !s_axi_bready;
|
||||||
|
|
||||||
|
case (write_state_reg)
|
||||||
|
WRITE_STATE_IDLE: begin
|
||||||
|
s_axi_awready_next = 1'b1;
|
||||||
|
|
||||||
|
if (s_axi_awready && s_axi_awvalid) begin
|
||||||
|
write_id_next = s_axi_awid;
|
||||||
|
write_addr_next = s_axi_awaddr;
|
||||||
|
write_count_next = s_axi_awlen;
|
||||||
|
write_size_next = s_axi_awsize < $clog2(STRB_WIDTH) ? s_axi_awsize : $clog2(STRB_WIDTH);
|
||||||
|
write_burst_next = s_axi_awburst;
|
||||||
|
|
||||||
|
s_axi_awready_next = 1'b0;
|
||||||
|
s_axi_wready_next = 1'b1;
|
||||||
|
write_state_next = WRITE_STATE_BURST;
|
||||||
|
end else begin
|
||||||
|
write_state_next = WRITE_STATE_IDLE;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
WRITE_STATE_BURST: begin
|
||||||
|
s_axi_wready_next = 1'b1;
|
||||||
|
|
||||||
|
if (s_axi_wready && s_axi_wvalid) begin
|
||||||
|
mem_wr_en = 1'b1;
|
||||||
|
if (write_burst_reg != 2'b00) begin
|
||||||
|
write_addr_next = write_addr_reg + (1 << write_size_reg);
|
||||||
|
end
|
||||||
|
write_count_next = write_count_reg - 1;
|
||||||
|
if (write_count_reg > 0) begin
|
||||||
|
write_state_next = WRITE_STATE_BURST;
|
||||||
|
end else begin
|
||||||
|
s_axi_wready_next = 1'b0;
|
||||||
|
if (s_axi_bready || !s_axi_bvalid) begin
|
||||||
|
s_axi_bid_next = write_id_reg;
|
||||||
|
s_axi_bvalid_next = 1'b1;
|
||||||
|
s_axi_awready_next = 1'b1;
|
||||||
|
write_state_next = WRITE_STATE_IDLE;
|
||||||
|
end else begin
|
||||||
|
write_state_next = WRITE_STATE_RESP;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end else begin
|
||||||
|
write_state_next = WRITE_STATE_BURST;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
WRITE_STATE_RESP: begin
|
||||||
|
if (s_axi_bready || !s_axi_bvalid) begin
|
||||||
|
s_axi_bid_next = write_id_reg;
|
||||||
|
s_axi_bvalid_next = 1'b1;
|
||||||
|
s_axi_awready_next = 1'b1;
|
||||||
|
write_state_next = WRITE_STATE_IDLE;
|
||||||
|
end else begin
|
||||||
|
write_state_next = WRITE_STATE_RESP;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
if (rst) begin
|
||||||
|
write_state_reg <= WRITE_STATE_IDLE;
|
||||||
|
s_axi_awready_reg <= 1'b0;
|
||||||
|
s_axi_wready_reg <= 1'b0;
|
||||||
|
s_axi_bvalid_reg <= 1'b0;
|
||||||
|
end else begin
|
||||||
|
write_state_reg <= write_state_next;
|
||||||
|
s_axi_awready_reg <= s_axi_awready_next;
|
||||||
|
s_axi_wready_reg <= s_axi_wready_next;
|
||||||
|
s_axi_bvalid_reg <= s_axi_bvalid_next;
|
||||||
|
end
|
||||||
|
|
||||||
|
write_id_reg <= write_id_next;
|
||||||
|
write_addr_reg <= write_addr_next;
|
||||||
|
write_count_reg <= write_count_next;
|
||||||
|
write_size_reg <= write_size_next;
|
||||||
|
write_burst_reg <= write_burst_next;
|
||||||
|
|
||||||
|
s_axi_bid_reg <= s_axi_bid_next;
|
||||||
|
|
||||||
|
for (i = 0; i < WORD_WIDTH; i = i + 1) begin
|
||||||
|
if (mem_wr_en & s_axi_wstrb[i]) begin
|
||||||
|
mem[write_addr_valid][WORD_SIZE*i +: WORD_SIZE] <= s_axi_wdata[WORD_SIZE*i +: WORD_SIZE];
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
always @* begin
|
||||||
|
read_state_next = READ_STATE_IDLE;
|
||||||
|
|
||||||
|
mem_rd_en = 1'b0;
|
||||||
|
|
||||||
|
s_axi_rid_next = s_axi_rid_reg;
|
||||||
|
s_axi_rlast_next = s_axi_rlast_reg;
|
||||||
|
s_axi_rvalid_next = s_axi_rvalid_reg && !(s_axi_rready || (PIPELINE_OUTPUT && !s_axi_rvalid_pipe_reg));
|
||||||
|
|
||||||
|
read_id_next = read_id_reg;
|
||||||
|
read_addr_next = read_addr_reg;
|
||||||
|
read_count_next = read_count_reg;
|
||||||
|
read_size_next = read_size_reg;
|
||||||
|
read_burst_next = read_burst_reg;
|
||||||
|
|
||||||
|
s_axi_arready_next = 1'b0;
|
||||||
|
|
||||||
|
case (read_state_reg)
|
||||||
|
READ_STATE_IDLE: begin
|
||||||
|
s_axi_arready_next = 1'b1;
|
||||||
|
|
||||||
|
if (s_axi_arready && s_axi_arvalid) begin
|
||||||
|
read_id_next = s_axi_arid;
|
||||||
|
read_addr_next = s_axi_araddr;
|
||||||
|
read_count_next = s_axi_arlen;
|
||||||
|
read_size_next = s_axi_arsize < $clog2(STRB_WIDTH) ? s_axi_arsize : $clog2(STRB_WIDTH);
|
||||||
|
read_burst_next = s_axi_arburst;
|
||||||
|
|
||||||
|
s_axi_arready_next = 1'b0;
|
||||||
|
read_state_next = READ_STATE_BURST;
|
||||||
|
end else begin
|
||||||
|
read_state_next = READ_STATE_IDLE;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
READ_STATE_BURST: begin
|
||||||
|
if (s_axi_rready || (PIPELINE_OUTPUT && !s_axi_rvalid_pipe_reg) || !s_axi_rvalid_reg) begin
|
||||||
|
mem_rd_en = 1'b1;
|
||||||
|
s_axi_rvalid_next = 1'b1;
|
||||||
|
s_axi_rid_next = read_id_reg;
|
||||||
|
s_axi_rlast_next = read_count_reg == 0;
|
||||||
|
if (read_burst_reg != 2'b00) begin
|
||||||
|
read_addr_next = read_addr_reg + (1 << read_size_reg);
|
||||||
|
end
|
||||||
|
read_count_next = read_count_reg - 1;
|
||||||
|
if (read_count_reg > 0) begin
|
||||||
|
read_state_next = READ_STATE_BURST;
|
||||||
|
end else begin
|
||||||
|
s_axi_arready_next = 1'b1;
|
||||||
|
read_state_next = READ_STATE_IDLE;
|
||||||
|
end
|
||||||
|
end else begin
|
||||||
|
read_state_next = READ_STATE_BURST;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
if (rst) begin
|
||||||
|
read_state_reg <= READ_STATE_IDLE;
|
||||||
|
s_axi_arready_reg <= 1'b0;
|
||||||
|
s_axi_rvalid_reg <= 1'b0;
|
||||||
|
s_axi_rvalid_pipe_reg <= 1'b0;
|
||||||
|
end else begin
|
||||||
|
read_state_reg <= read_state_next;
|
||||||
|
s_axi_arready_reg <= s_axi_arready_next;
|
||||||
|
s_axi_rvalid_reg <= s_axi_rvalid_next;
|
||||||
|
|
||||||
|
if (!s_axi_rvalid_pipe_reg || s_axi_rready) begin
|
||||||
|
s_axi_rvalid_pipe_reg <= s_axi_rvalid_reg;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
read_id_reg <= read_id_next;
|
||||||
|
read_addr_reg <= read_addr_next;
|
||||||
|
read_count_reg <= read_count_next;
|
||||||
|
read_size_reg <= read_size_next;
|
||||||
|
read_burst_reg <= read_burst_next;
|
||||||
|
|
||||||
|
s_axi_rid_reg <= s_axi_rid_next;
|
||||||
|
s_axi_rlast_reg <= s_axi_rlast_next;
|
||||||
|
|
||||||
|
if (mem_rd_en) begin
|
||||||
|
s_axi_rdata_reg <= mem[read_addr_valid];
|
||||||
|
end
|
||||||
|
|
||||||
|
if (!s_axi_rvalid_pipe_reg || s_axi_rready) begin
|
||||||
|
s_axi_rid_pipe_reg <= s_axi_rid_reg;
|
||||||
|
s_axi_rdata_pipe_reg <= s_axi_rdata_reg;
|
||||||
|
s_axi_rlast_pipe_reg <= s_axi_rlast_reg;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
endmodule
|
||||||
264
example/ExaNIC_X10/fpga/rtl/axis_register.v
Normal file
264
example/ExaNIC_X10/fpga/rtl/axis_register.v
Normal file
@ -0,0 +1,264 @@
|
|||||||
|
/*
|
||||||
|
|
||||||
|
Copyright (c) 2014-2018 Alex Forencich
|
||||||
|
|
||||||
|
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||||
|
of this software and associated documentation files (the "Software"), to deal
|
||||||
|
in the Software without restriction, including without limitation the rights
|
||||||
|
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||||
|
copies of the Software, and to permit persons to whom the Software is
|
||||||
|
furnished to do so, subject to the following conditions:
|
||||||
|
|
||||||
|
The above copyright notice and this permission notice shall be included in
|
||||||
|
all copies or substantial portions of the Software.
|
||||||
|
|
||||||
|
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||||
|
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||||
|
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||||
|
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||||
|
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||||
|
THE SOFTWARE.
|
||||||
|
|
||||||
|
*/
|
||||||
|
|
||||||
|
// Language: Verilog 2001
|
||||||
|
|
||||||
|
`timescale 1ns / 1ps
|
||||||
|
|
||||||
|
/*
|
||||||
|
* AXI4-Stream register
|
||||||
|
*/
|
||||||
|
module axis_register #
|
||||||
|
(
|
||||||
|
parameter DATA_WIDTH = 8,
|
||||||
|
parameter KEEP_ENABLE = (DATA_WIDTH>8),
|
||||||
|
parameter KEEP_WIDTH = (DATA_WIDTH/8),
|
||||||
|
parameter LAST_ENABLE = 1,
|
||||||
|
parameter ID_ENABLE = 0,
|
||||||
|
parameter ID_WIDTH = 8,
|
||||||
|
parameter DEST_ENABLE = 0,
|
||||||
|
parameter DEST_WIDTH = 8,
|
||||||
|
parameter USER_ENABLE = 1,
|
||||||
|
parameter USER_WIDTH = 1,
|
||||||
|
parameter REG_TYPE = 2
|
||||||
|
)
|
||||||
|
(
|
||||||
|
input wire clk,
|
||||||
|
input wire rst,
|
||||||
|
|
||||||
|
/*
|
||||||
|
* AXI Stream input
|
||||||
|
*/
|
||||||
|
input wire [DATA_WIDTH-1:0] s_axis_tdata,
|
||||||
|
input wire [KEEP_WIDTH-1:0] s_axis_tkeep,
|
||||||
|
input wire s_axis_tvalid,
|
||||||
|
output wire s_axis_tready,
|
||||||
|
input wire s_axis_tlast,
|
||||||
|
input wire [ID_WIDTH-1:0] s_axis_tid,
|
||||||
|
input wire [DEST_WIDTH-1:0] s_axis_tdest,
|
||||||
|
input wire [USER_WIDTH-1:0] s_axis_tuser,
|
||||||
|
|
||||||
|
/*
|
||||||
|
* AXI Stream output
|
||||||
|
*/
|
||||||
|
output wire [DATA_WIDTH-1:0] m_axis_tdata,
|
||||||
|
output wire [KEEP_WIDTH-1:0] m_axis_tkeep,
|
||||||
|
output wire m_axis_tvalid,
|
||||||
|
input wire m_axis_tready,
|
||||||
|
output wire m_axis_tlast,
|
||||||
|
output wire [ID_WIDTH-1:0] m_axis_tid,
|
||||||
|
output wire [DEST_WIDTH-1:0] m_axis_tdest,
|
||||||
|
output wire [USER_WIDTH-1:0] m_axis_tuser
|
||||||
|
);
|
||||||
|
|
||||||
|
generate
|
||||||
|
|
||||||
|
if (REG_TYPE > 1) begin
|
||||||
|
// skid buffer, no bubble cycles
|
||||||
|
|
||||||
|
// datapath registers
|
||||||
|
reg s_axis_tready_reg = 1'b0;
|
||||||
|
|
||||||
|
reg [DATA_WIDTH-1:0] m_axis_tdata_reg = {DATA_WIDTH{1'b0}};
|
||||||
|
reg [KEEP_WIDTH-1:0] m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
|
||||||
|
reg m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
|
||||||
|
reg m_axis_tlast_reg = 1'b0;
|
||||||
|
reg [ID_WIDTH-1:0] m_axis_tid_reg = {ID_WIDTH{1'b0}};
|
||||||
|
reg [DEST_WIDTH-1:0] m_axis_tdest_reg = {DEST_WIDTH{1'b0}};
|
||||||
|
reg [USER_WIDTH-1:0] m_axis_tuser_reg = {USER_WIDTH{1'b0}};
|
||||||
|
|
||||||
|
reg [DATA_WIDTH-1:0] temp_m_axis_tdata_reg = {DATA_WIDTH{1'b0}};
|
||||||
|
reg [KEEP_WIDTH-1:0] temp_m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
|
||||||
|
reg temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next;
|
||||||
|
reg temp_m_axis_tlast_reg = 1'b0;
|
||||||
|
reg [ID_WIDTH-1:0] temp_m_axis_tid_reg = {ID_WIDTH{1'b0}};
|
||||||
|
reg [DEST_WIDTH-1:0] temp_m_axis_tdest_reg = {DEST_WIDTH{1'b0}};
|
||||||
|
reg [USER_WIDTH-1:0] temp_m_axis_tuser_reg = {USER_WIDTH{1'b0}};
|
||||||
|
|
||||||
|
// datapath control
|
||||||
|
reg store_axis_input_to_output;
|
||||||
|
reg store_axis_input_to_temp;
|
||||||
|
reg store_axis_temp_to_output;
|
||||||
|
|
||||||
|
assign s_axis_tready = s_axis_tready_reg;
|
||||||
|
|
||||||
|
assign m_axis_tdata = m_axis_tdata_reg;
|
||||||
|
assign m_axis_tkeep = KEEP_ENABLE ? m_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
|
||||||
|
assign m_axis_tvalid = m_axis_tvalid_reg;
|
||||||
|
assign m_axis_tlast = LAST_ENABLE ? m_axis_tlast_reg : 1'b1;
|
||||||
|
assign m_axis_tid = ID_ENABLE ? m_axis_tid_reg : {ID_WIDTH{1'b0}};
|
||||||
|
assign m_axis_tdest = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}};
|
||||||
|
assign m_axis_tuser = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}};
|
||||||
|
|
||||||
|
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
|
||||||
|
wire s_axis_tready_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !s_axis_tvalid));
|
||||||
|
|
||||||
|
always @* begin
|
||||||
|
// transfer sink ready state to source
|
||||||
|
m_axis_tvalid_next = m_axis_tvalid_reg;
|
||||||
|
temp_m_axis_tvalid_next = temp_m_axis_tvalid_reg;
|
||||||
|
|
||||||
|
store_axis_input_to_output = 1'b0;
|
||||||
|
store_axis_input_to_temp = 1'b0;
|
||||||
|
store_axis_temp_to_output = 1'b0;
|
||||||
|
|
||||||
|
if (s_axis_tready_reg) begin
|
||||||
|
// input is ready
|
||||||
|
if (m_axis_tready || !m_axis_tvalid_reg) begin
|
||||||
|
// output is ready or currently not valid, transfer data to output
|
||||||
|
m_axis_tvalid_next = s_axis_tvalid;
|
||||||
|
store_axis_input_to_output = 1'b1;
|
||||||
|
end else begin
|
||||||
|
// output is not ready, store input in temp
|
||||||
|
temp_m_axis_tvalid_next = s_axis_tvalid;
|
||||||
|
store_axis_input_to_temp = 1'b1;
|
||||||
|
end
|
||||||
|
end else if (m_axis_tready) begin
|
||||||
|
// input is not ready, but output is ready
|
||||||
|
m_axis_tvalid_next = temp_m_axis_tvalid_reg;
|
||||||
|
temp_m_axis_tvalid_next = 1'b0;
|
||||||
|
store_axis_temp_to_output = 1'b1;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
if (rst) begin
|
||||||
|
s_axis_tready_reg <= 1'b0;
|
||||||
|
m_axis_tvalid_reg <= 1'b0;
|
||||||
|
temp_m_axis_tvalid_reg <= 1'b0;
|
||||||
|
end else begin
|
||||||
|
s_axis_tready_reg <= s_axis_tready_early;
|
||||||
|
m_axis_tvalid_reg <= m_axis_tvalid_next;
|
||||||
|
temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
|
||||||
|
end
|
||||||
|
|
||||||
|
// datapath
|
||||||
|
if (store_axis_input_to_output) begin
|
||||||
|
m_axis_tdata_reg <= s_axis_tdata;
|
||||||
|
m_axis_tkeep_reg <= s_axis_tkeep;
|
||||||
|
m_axis_tlast_reg <= s_axis_tlast;
|
||||||
|
m_axis_tid_reg <= s_axis_tid;
|
||||||
|
m_axis_tdest_reg <= s_axis_tdest;
|
||||||
|
m_axis_tuser_reg <= s_axis_tuser;
|
||||||
|
end else if (store_axis_temp_to_output) begin
|
||||||
|
m_axis_tdata_reg <= temp_m_axis_tdata_reg;
|
||||||
|
m_axis_tkeep_reg <= temp_m_axis_tkeep_reg;
|
||||||
|
m_axis_tlast_reg <= temp_m_axis_tlast_reg;
|
||||||
|
m_axis_tid_reg <= temp_m_axis_tid_reg;
|
||||||
|
m_axis_tdest_reg <= temp_m_axis_tdest_reg;
|
||||||
|
m_axis_tuser_reg <= temp_m_axis_tuser_reg;
|
||||||
|
end
|
||||||
|
|
||||||
|
if (store_axis_input_to_temp) begin
|
||||||
|
temp_m_axis_tdata_reg <= s_axis_tdata;
|
||||||
|
temp_m_axis_tkeep_reg <= s_axis_tkeep;
|
||||||
|
temp_m_axis_tlast_reg <= s_axis_tlast;
|
||||||
|
temp_m_axis_tid_reg <= s_axis_tid;
|
||||||
|
temp_m_axis_tdest_reg <= s_axis_tdest;
|
||||||
|
temp_m_axis_tuser_reg <= s_axis_tuser;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
end else if (REG_TYPE == 1) begin
|
||||||
|
// simple register, inserts bubble cycles
|
||||||
|
|
||||||
|
// datapath registers
|
||||||
|
reg s_axis_tready_reg = 1'b0;
|
||||||
|
|
||||||
|
reg [DATA_WIDTH-1:0] m_axis_tdata_reg = {DATA_WIDTH{1'b0}};
|
||||||
|
reg [KEEP_WIDTH-1:0] m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
|
||||||
|
reg m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
|
||||||
|
reg m_axis_tlast_reg = 1'b0;
|
||||||
|
reg [ID_WIDTH-1:0] m_axis_tid_reg = {ID_WIDTH{1'b0}};
|
||||||
|
reg [DEST_WIDTH-1:0] m_axis_tdest_reg = {DEST_WIDTH{1'b0}};
|
||||||
|
reg [USER_WIDTH-1:0] m_axis_tuser_reg = {USER_WIDTH{1'b0}};
|
||||||
|
|
||||||
|
// datapath control
|
||||||
|
reg store_axis_input_to_output;
|
||||||
|
|
||||||
|
assign s_axis_tready = s_axis_tready_reg;
|
||||||
|
|
||||||
|
assign m_axis_tdata = m_axis_tdata_reg;
|
||||||
|
assign m_axis_tkeep = KEEP_ENABLE ? m_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
|
||||||
|
assign m_axis_tvalid = m_axis_tvalid_reg;
|
||||||
|
assign m_axis_tlast = LAST_ENABLE ? m_axis_tlast_reg : 1'b1;
|
||||||
|
assign m_axis_tid = ID_ENABLE ? m_axis_tid_reg : {ID_WIDTH{1'b0}};
|
||||||
|
assign m_axis_tdest = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}};
|
||||||
|
assign m_axis_tuser = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}};
|
||||||
|
|
||||||
|
// enable ready input next cycle if output buffer will be empty
|
||||||
|
wire s_axis_tready_early = !m_axis_tvalid_next;
|
||||||
|
|
||||||
|
always @* begin
|
||||||
|
// transfer sink ready state to source
|
||||||
|
m_axis_tvalid_next = m_axis_tvalid_reg;
|
||||||
|
|
||||||
|
store_axis_input_to_output = 1'b0;
|
||||||
|
|
||||||
|
if (s_axis_tready_reg) begin
|
||||||
|
m_axis_tvalid_next = s_axis_tvalid;
|
||||||
|
store_axis_input_to_output = 1'b1;
|
||||||
|
end else if (m_axis_tready) begin
|
||||||
|
m_axis_tvalid_next = 1'b0;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
if (rst) begin
|
||||||
|
s_axis_tready_reg <= 1'b0;
|
||||||
|
m_axis_tvalid_reg <= 1'b0;
|
||||||
|
end else begin
|
||||||
|
s_axis_tready_reg <= s_axis_tready_early;
|
||||||
|
m_axis_tvalid_reg <= m_axis_tvalid_next;
|
||||||
|
end
|
||||||
|
|
||||||
|
// datapath
|
||||||
|
if (store_axis_input_to_output) begin
|
||||||
|
m_axis_tdata_reg <= s_axis_tdata;
|
||||||
|
m_axis_tkeep_reg <= s_axis_tkeep;
|
||||||
|
m_axis_tlast_reg <= s_axis_tlast;
|
||||||
|
m_axis_tid_reg <= s_axis_tid;
|
||||||
|
m_axis_tdest_reg <= s_axis_tdest;
|
||||||
|
m_axis_tuser_reg <= s_axis_tuser;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
end else begin
|
||||||
|
// bypass
|
||||||
|
|
||||||
|
assign m_axis_tdata = s_axis_tdata;
|
||||||
|
assign m_axis_tkeep = KEEP_ENABLE ? s_axis_tkeep : {KEEP_WIDTH{1'b1}};
|
||||||
|
assign m_axis_tvalid = s_axis_tvalid;
|
||||||
|
assign m_axis_tlast = LAST_ENABLE ? s_axis_tlast : 1'b1;
|
||||||
|
assign m_axis_tid = ID_ENABLE ? s_axis_tid : {ID_WIDTH{1'b0}};
|
||||||
|
assign m_axis_tdest = DEST_ENABLE ? s_axis_tdest : {DEST_WIDTH{1'b0}};
|
||||||
|
assign m_axis_tuser = USER_ENABLE ? s_axis_tuser : {USER_WIDTH{1'b0}};
|
||||||
|
|
||||||
|
assign s_axis_tready = m_axis_tready;
|
||||||
|
|
||||||
|
end
|
||||||
|
|
||||||
|
endgenerate
|
||||||
|
|
||||||
|
endmodule
|
||||||
89
example/ExaNIC_X10/fpga/rtl/debounce_switch.v
Normal file
89
example/ExaNIC_X10/fpga/rtl/debounce_switch.v
Normal file
@ -0,0 +1,89 @@
|
|||||||
|
/*
|
||||||
|
|
||||||
|
Copyright (c) 2014-2018 Alex Forencich
|
||||||
|
|
||||||
|
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||||
|
of this software and associated documentation files (the "Software"), to deal
|
||||||
|
in the Software without restriction, including without limitation the rights
|
||||||
|
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||||
|
copies of the Software, and to permit persons to whom the Software is
|
||||||
|
furnished to do so, subject to the following conditions:
|
||||||
|
|
||||||
|
The above copyright notice and this permission notice shall be included in
|
||||||
|
all copies or substantial portions of the Software.
|
||||||
|
|
||||||
|
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||||
|
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||||
|
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||||
|
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||||
|
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||||
|
THE SOFTWARE.
|
||||||
|
|
||||||
|
*/
|
||||||
|
|
||||||
|
// Language: Verilog-2001
|
||||||
|
|
||||||
|
`timescale 1 ns / 1 ps
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Synchronizes switch and button inputs with a slow sampled shift register
|
||||||
|
*/
|
||||||
|
module debounce_switch #(
|
||||||
|
parameter WIDTH=1, // width of the input and output signals
|
||||||
|
parameter N=3, // length of shift register
|
||||||
|
parameter RATE=125000 // clock division factor
|
||||||
|
)(
|
||||||
|
input wire clk,
|
||||||
|
input wire rst,
|
||||||
|
input wire [WIDTH-1:0] in,
|
||||||
|
output wire [WIDTH-1:0] out
|
||||||
|
);
|
||||||
|
|
||||||
|
reg [23:0] cnt_reg = 24'd0;
|
||||||
|
|
||||||
|
reg [N-1:0] debounce_reg[WIDTH-1:0];
|
||||||
|
|
||||||
|
reg [WIDTH-1:0] state;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* The synchronized output is the state register
|
||||||
|
*/
|
||||||
|
assign out = state;
|
||||||
|
|
||||||
|
integer k;
|
||||||
|
|
||||||
|
always @(posedge clk or posedge rst) begin
|
||||||
|
if (rst) begin
|
||||||
|
cnt_reg <= 0;
|
||||||
|
state <= 0;
|
||||||
|
|
||||||
|
for (k = 0; k < WIDTH; k = k + 1) begin
|
||||||
|
debounce_reg[k] <= 0;
|
||||||
|
end
|
||||||
|
end else begin
|
||||||
|
if (cnt_reg < RATE) begin
|
||||||
|
cnt_reg <= cnt_reg + 24'd1;
|
||||||
|
end else begin
|
||||||
|
cnt_reg <= 24'd0;
|
||||||
|
end
|
||||||
|
|
||||||
|
if (cnt_reg == 24'd0) begin
|
||||||
|
for (k = 0; k < WIDTH; k = k + 1) begin
|
||||||
|
debounce_reg[k] <= {debounce_reg[k][N-2:0], in[k]};
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
for (k = 0; k < WIDTH; k = k + 1) begin
|
||||||
|
if (|debounce_reg[k] == 0) begin
|
||||||
|
state[k] <= 0;
|
||||||
|
end else if (&debounce_reg[k] == 1) begin
|
||||||
|
state[k] <= 1;
|
||||||
|
end else begin
|
||||||
|
state[k] <= state[k];
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
endmodule
|
||||||
402
example/ExaNIC_X10/fpga/rtl/fpga.v
Normal file
402
example/ExaNIC_X10/fpga/rtl/fpga.v
Normal file
@ -0,0 +1,402 @@
|
|||||||
|
/*
|
||||||
|
|
||||||
|
Copyright (c) 2018 Alex Forencich
|
||||||
|
|
||||||
|
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||||
|
of this software and associated documentation files (the "Software"), to deal
|
||||||
|
in the Software without restriction, including without limitation the rights
|
||||||
|
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||||
|
copies of the Software, and to permit persons to whom the Software is
|
||||||
|
furnished to do so, subject to the following conditions:
|
||||||
|
|
||||||
|
The above copyright notice and this permission notice shall be included in
|
||||||
|
all copies or substantial portions of the Software.
|
||||||
|
|
||||||
|
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||||
|
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||||
|
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||||
|
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||||
|
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||||
|
THE SOFTWARE.
|
||||||
|
|
||||||
|
*/
|
||||||
|
|
||||||
|
// Language: Verilog 2001
|
||||||
|
|
||||||
|
`timescale 1ns / 1ps
|
||||||
|
|
||||||
|
/*
|
||||||
|
* FPGA top-level module
|
||||||
|
*/
|
||||||
|
module fpga (
|
||||||
|
/*
|
||||||
|
* GPIO
|
||||||
|
*/
|
||||||
|
output wire [1:0] sfp_1_led,
|
||||||
|
output wire [1:0] sfp_2_led,
|
||||||
|
output wire [1:0] sma_led,
|
||||||
|
|
||||||
|
/*
|
||||||
|
* PCI express
|
||||||
|
*/
|
||||||
|
input wire [7:0] pcie_rx_p,
|
||||||
|
input wire [7:0] pcie_rx_n,
|
||||||
|
output wire [7:0] pcie_tx_p,
|
||||||
|
output wire [7:0] pcie_tx_n,
|
||||||
|
input wire pcie_mgt_refclk_p,
|
||||||
|
input wire pcie_mgt_refclk_n,
|
||||||
|
input wire pcie_reset_n
|
||||||
|
);
|
||||||
|
|
||||||
|
parameter AXIS_PCIE_DATA_WIDTH = 256;
|
||||||
|
parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32);
|
||||||
|
|
||||||
|
// PCIe
|
||||||
|
wire pcie_user_clk;
|
||||||
|
wire pcie_user_reset;
|
||||||
|
|
||||||
|
wire pcie_sys_clk;
|
||||||
|
wire pcie_sys_clk_gt;
|
||||||
|
|
||||||
|
IBUFDS_GTE3 #(
|
||||||
|
.REFCLK_HROW_CK_SEL(2'b00)
|
||||||
|
)
|
||||||
|
ibufds_gte3_pcie_mgt_refclk_inst (
|
||||||
|
.I (pcie_mgt_refclk_p),
|
||||||
|
.IB (pcie_mgt_refclk_n),
|
||||||
|
.CEB (1'b0),
|
||||||
|
.O (pcie_sys_clk_gt),
|
||||||
|
.ODIV2 (pcie_sys_clk)
|
||||||
|
);
|
||||||
|
|
||||||
|
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rq_tdata;
|
||||||
|
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rq_tkeep;
|
||||||
|
wire axis_rq_tlast;
|
||||||
|
wire axis_rq_tready;
|
||||||
|
wire [59:0] axis_rq_tuser;
|
||||||
|
wire axis_rq_tvalid;
|
||||||
|
|
||||||
|
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rc_tdata;
|
||||||
|
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rc_tkeep;
|
||||||
|
wire axis_rc_tlast;
|
||||||
|
wire axis_rc_tready;
|
||||||
|
wire [74:0] axis_rc_tuser;
|
||||||
|
wire axis_rc_tvalid;
|
||||||
|
|
||||||
|
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata;
|
||||||
|
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep;
|
||||||
|
wire axis_cq_tlast;
|
||||||
|
wire axis_cq_tready;
|
||||||
|
wire [84:0] axis_cq_tuser;
|
||||||
|
wire axis_cq_tvalid;
|
||||||
|
|
||||||
|
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata;
|
||||||
|
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep;
|
||||||
|
wire axis_cc_tlast;
|
||||||
|
wire axis_cc_tready;
|
||||||
|
wire [32:0] axis_cc_tuser;
|
||||||
|
wire axis_cc_tvalid;
|
||||||
|
|
||||||
|
// ila_0 rq_ila (
|
||||||
|
// .clk(pcie_user_clk),
|
||||||
|
// .probe0(axis_rq_tdata),
|
||||||
|
// .probe1(axis_rq_tkeep),
|
||||||
|
// .probe2(axis_rq_tlast),
|
||||||
|
// .probe3(axis_rq_tready),
|
||||||
|
// .probe4(axis_rq_tuser),
|
||||||
|
// .probe5(axis_rq_tvalid)
|
||||||
|
// );
|
||||||
|
|
||||||
|
// ila_0 rc_ila (
|
||||||
|
// .clk(pcie_user_clk),
|
||||||
|
// .probe0(axis_rc_tdata),
|
||||||
|
// .probe1(axis_rc_tkeep),
|
||||||
|
// .probe2(axis_rc_tlast),
|
||||||
|
// .probe3(axis_rc_tready),
|
||||||
|
// .probe4(axis_rc_tuser),
|
||||||
|
// .probe5(axis_rc_tvalid)
|
||||||
|
// );
|
||||||
|
|
||||||
|
wire [2:0] cfg_max_payload;
|
||||||
|
wire [2:0] cfg_max_read_req;
|
||||||
|
|
||||||
|
wire [18:0] cfg_mgmt_addr;
|
||||||
|
wire cfg_mgmt_write;
|
||||||
|
wire [31:0] cfg_mgmt_write_data;
|
||||||
|
wire [3:0] cfg_mgmt_byte_enable;
|
||||||
|
wire cfg_mgmt_read;
|
||||||
|
wire [31:0] cfg_mgmt_read_data;
|
||||||
|
wire cfg_mgmt_read_write_done;
|
||||||
|
|
||||||
|
wire [3:0] cfg_interrupt_msi_enable;
|
||||||
|
wire [7:0] cfg_interrupt_msi_vf_enable;
|
||||||
|
wire [11:0] cfg_interrupt_msi_mmenable;
|
||||||
|
wire cfg_interrupt_msi_mask_update;
|
||||||
|
wire [31:0] cfg_interrupt_msi_data;
|
||||||
|
wire [3:0] cfg_interrupt_msi_select;
|
||||||
|
wire [31:0] cfg_interrupt_msi_int;
|
||||||
|
wire [31:0] cfg_interrupt_msi_pending_status;
|
||||||
|
wire cfg_interrupt_msi_pending_status_data_enable;
|
||||||
|
wire [3:0] cfg_interrupt_msi_pending_status_function_num;
|
||||||
|
wire cfg_interrupt_msi_sent;
|
||||||
|
wire cfg_interrupt_msi_fail;
|
||||||
|
wire [2:0] cfg_interrupt_msi_attr;
|
||||||
|
wire cfg_interrupt_msi_tph_present;
|
||||||
|
wire [1:0] cfg_interrupt_msi_tph_type;
|
||||||
|
wire [8:0] cfg_interrupt_msi_tph_st_tag;
|
||||||
|
wire [3:0] cfg_interrupt_msi_function_number;
|
||||||
|
|
||||||
|
wire status_error_cor;
|
||||||
|
wire status_error_uncor;
|
||||||
|
|
||||||
|
pcie3_ultrascale_0
|
||||||
|
pcie3_ultrascale_inst (
|
||||||
|
.pci_exp_txn(pcie_tx_n),
|
||||||
|
.pci_exp_txp(pcie_tx_p),
|
||||||
|
.pci_exp_rxn(pcie_rx_n),
|
||||||
|
.pci_exp_rxp(pcie_rx_p),
|
||||||
|
.user_clk(pcie_user_clk),
|
||||||
|
.user_reset(pcie_user_reset),
|
||||||
|
.user_lnk_up(),
|
||||||
|
|
||||||
|
.s_axis_rq_tdata(axis_rq_tdata),
|
||||||
|
.s_axis_rq_tkeep(axis_rq_tkeep),
|
||||||
|
.s_axis_rq_tlast(axis_rq_tlast),
|
||||||
|
.s_axis_rq_tready(axis_rq_tready),
|
||||||
|
.s_axis_rq_tuser(axis_rq_tuser),
|
||||||
|
.s_axis_rq_tvalid(axis_rq_tvalid),
|
||||||
|
|
||||||
|
.m_axis_rc_tdata(axis_rc_tdata),
|
||||||
|
.m_axis_rc_tkeep(axis_rc_tkeep),
|
||||||
|
.m_axis_rc_tlast(axis_rc_tlast),
|
||||||
|
.m_axis_rc_tready(axis_rc_tready),
|
||||||
|
.m_axis_rc_tuser(axis_rc_tuser),
|
||||||
|
.m_axis_rc_tvalid(axis_rc_tvalid),
|
||||||
|
|
||||||
|
.m_axis_cq_tdata(axis_cq_tdata),
|
||||||
|
.m_axis_cq_tkeep(axis_cq_tkeep),
|
||||||
|
.m_axis_cq_tlast(axis_cq_tlast),
|
||||||
|
.m_axis_cq_tready(axis_cq_tready),
|
||||||
|
.m_axis_cq_tuser(axis_cq_tuser),
|
||||||
|
.m_axis_cq_tvalid(axis_cq_tvalid),
|
||||||
|
|
||||||
|
.s_axis_cc_tdata(axis_cc_tdata),
|
||||||
|
.s_axis_cc_tkeep(axis_cc_tkeep),
|
||||||
|
.s_axis_cc_tlast(axis_cc_tlast),
|
||||||
|
.s_axis_cc_tready(axis_cc_tready),
|
||||||
|
.s_axis_cc_tuser(axis_cc_tuser),
|
||||||
|
.s_axis_cc_tvalid(axis_cc_tvalid),
|
||||||
|
|
||||||
|
.pcie_rq_seq_num(),
|
||||||
|
.pcie_rq_seq_num_vld(),
|
||||||
|
.pcie_rq_tag(),
|
||||||
|
.pcie_rq_tag_av(),
|
||||||
|
.pcie_rq_tag_vld(),
|
||||||
|
|
||||||
|
.pcie_tfc_nph_av(),
|
||||||
|
.pcie_tfc_npd_av(),
|
||||||
|
|
||||||
|
.pcie_cq_np_req(1'b1),
|
||||||
|
.pcie_cq_np_req_count(),
|
||||||
|
|
||||||
|
.cfg_phy_link_down(),
|
||||||
|
.cfg_phy_link_status(),
|
||||||
|
.cfg_negotiated_width(),
|
||||||
|
.cfg_current_speed(),
|
||||||
|
.cfg_max_payload(cfg_max_payload),
|
||||||
|
.cfg_max_read_req(cfg_max_read_req),
|
||||||
|
.cfg_function_status(),
|
||||||
|
.cfg_function_power_state(),
|
||||||
|
.cfg_vf_status(),
|
||||||
|
.cfg_vf_power_state(),
|
||||||
|
.cfg_link_power_state(),
|
||||||
|
|
||||||
|
.cfg_mgmt_addr(cfg_mgmt_addr),
|
||||||
|
.cfg_mgmt_write(cfg_mgmt_write),
|
||||||
|
.cfg_mgmt_write_data(cfg_mgmt_write_data),
|
||||||
|
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
|
||||||
|
.cfg_mgmt_read(cfg_mgmt_read),
|
||||||
|
.cfg_mgmt_read_data(cfg_mgmt_read_data),
|
||||||
|
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
|
||||||
|
.cfg_mgmt_type1_cfg_reg_access(1'b0),
|
||||||
|
|
||||||
|
.cfg_err_cor_out(),
|
||||||
|
.cfg_err_nonfatal_out(),
|
||||||
|
.cfg_err_fatal_out(),
|
||||||
|
.cfg_local_error(),
|
||||||
|
.cfg_ltr_enable(),
|
||||||
|
.cfg_ltssm_state(),
|
||||||
|
.cfg_rcb_status(),
|
||||||
|
.cfg_dpa_substate_change(),
|
||||||
|
.cfg_obff_enable(),
|
||||||
|
.cfg_pl_status_change(),
|
||||||
|
.cfg_tph_requester_enable(),
|
||||||
|
.cfg_tph_st_mode(),
|
||||||
|
.cfg_vf_tph_requester_enable(),
|
||||||
|
.cfg_vf_tph_st_mode(),
|
||||||
|
|
||||||
|
.cfg_msg_received(),
|
||||||
|
.cfg_msg_received_data(),
|
||||||
|
.cfg_msg_received_type(),
|
||||||
|
.cfg_msg_transmit(1'b0),
|
||||||
|
.cfg_msg_transmit_type(3'd0),
|
||||||
|
.cfg_msg_transmit_data(32'd0),
|
||||||
|
.cfg_msg_transmit_done(),
|
||||||
|
|
||||||
|
.cfg_fc_ph(),
|
||||||
|
.cfg_fc_pd(),
|
||||||
|
.cfg_fc_nph(),
|
||||||
|
.cfg_fc_npd(),
|
||||||
|
.cfg_fc_cplh(),
|
||||||
|
.cfg_fc_cpld(),
|
||||||
|
.cfg_fc_sel(3'd0),
|
||||||
|
|
||||||
|
.cfg_per_func_status_control(3'd0),
|
||||||
|
.cfg_per_func_status_data(),
|
||||||
|
.cfg_per_function_number(4'd0),
|
||||||
|
.cfg_per_function_output_request(1'b0),
|
||||||
|
.cfg_per_function_update_done(),
|
||||||
|
|
||||||
|
.cfg_dsn(64'd0),
|
||||||
|
|
||||||
|
.cfg_power_state_change_ack(1'b1),
|
||||||
|
.cfg_power_state_change_interrupt(),
|
||||||
|
|
||||||
|
.cfg_err_cor_in(status_error_cor),
|
||||||
|
.cfg_err_uncor_in(status_error_uncor),
|
||||||
|
.cfg_flr_in_process(),
|
||||||
|
.cfg_flr_done(4'd0),
|
||||||
|
.cfg_vf_flr_in_process(),
|
||||||
|
.cfg_vf_flr_done(8'd0),
|
||||||
|
|
||||||
|
.cfg_link_training_enable(1'b1),
|
||||||
|
|
||||||
|
.cfg_interrupt_int(4'd0),
|
||||||
|
.cfg_interrupt_pending(4'd0),
|
||||||
|
.cfg_interrupt_sent(),
|
||||||
|
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
|
||||||
|
.cfg_interrupt_msi_vf_enable(cfg_interrupt_msi_vf_enable),
|
||||||
|
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
|
||||||
|
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
|
||||||
|
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
|
||||||
|
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
|
||||||
|
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
|
||||||
|
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
|
||||||
|
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
|
||||||
|
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
|
||||||
|
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
|
||||||
|
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
|
||||||
|
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
|
||||||
|
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
|
||||||
|
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
|
||||||
|
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
|
||||||
|
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
|
||||||
|
|
||||||
|
.cfg_hot_reset_out(),
|
||||||
|
|
||||||
|
.cfg_config_space_enable(1'b1),
|
||||||
|
.cfg_req_pm_transition_l23_ready(1'b0),
|
||||||
|
.cfg_hot_reset_in(1'b0),
|
||||||
|
|
||||||
|
.cfg_ds_port_number(8'd0),
|
||||||
|
.cfg_ds_bus_number(8'd0),
|
||||||
|
.cfg_ds_device_number(5'd0),
|
||||||
|
.cfg_ds_function_number(3'd0),
|
||||||
|
|
||||||
|
.cfg_subsys_vend_id(16'h1234),
|
||||||
|
|
||||||
|
.sys_clk(pcie_sys_clk),
|
||||||
|
.sys_clk_gt(pcie_sys_clk_gt),
|
||||||
|
.sys_reset(pcie_reset_n),
|
||||||
|
.pcie_perstn1_in(1'b0),
|
||||||
|
.pcie_perstn0_out(),
|
||||||
|
.pcie_perstn1_out(),
|
||||||
|
|
||||||
|
.int_qpll1lock_out(),
|
||||||
|
.int_qpll1outrefclk_out(),
|
||||||
|
.int_qpll1outclk_out(),
|
||||||
|
.phy_rdy_out()
|
||||||
|
);
|
||||||
|
|
||||||
|
fpga_core #(
|
||||||
|
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH)
|
||||||
|
)
|
||||||
|
core_inst (
|
||||||
|
/*
|
||||||
|
* Clock: 250 MHz
|
||||||
|
* Synchronous reset
|
||||||
|
*/
|
||||||
|
.clk(pcie_user_clk),
|
||||||
|
.rst(pcie_user_reset),
|
||||||
|
/*
|
||||||
|
* GPIO
|
||||||
|
*/
|
||||||
|
.sfp_1_led(sfp_1_led),
|
||||||
|
.sfp_2_led(sfp_2_led),
|
||||||
|
.sma_led(sma_led),
|
||||||
|
/*
|
||||||
|
* PCIe
|
||||||
|
*/
|
||||||
|
.m_axis_rq_tdata(axis_rq_tdata),
|
||||||
|
.m_axis_rq_tkeep(axis_rq_tkeep),
|
||||||
|
.m_axis_rq_tlast(axis_rq_tlast),
|
||||||
|
.m_axis_rq_tready(axis_rq_tready),
|
||||||
|
.m_axis_rq_tuser(axis_rq_tuser),
|
||||||
|
.m_axis_rq_tvalid(axis_rq_tvalid),
|
||||||
|
|
||||||
|
.s_axis_rc_tdata(axis_rc_tdata),
|
||||||
|
.s_axis_rc_tkeep(axis_rc_tkeep),
|
||||||
|
.s_axis_rc_tlast(axis_rc_tlast),
|
||||||
|
.s_axis_rc_tready(axis_rc_tready),
|
||||||
|
.s_axis_rc_tuser(axis_rc_tuser),
|
||||||
|
.s_axis_rc_tvalid(axis_rc_tvalid),
|
||||||
|
|
||||||
|
.s_axis_cq_tdata(axis_cq_tdata),
|
||||||
|
.s_axis_cq_tkeep(axis_cq_tkeep),
|
||||||
|
.s_axis_cq_tlast(axis_cq_tlast),
|
||||||
|
.s_axis_cq_tready(axis_cq_tready),
|
||||||
|
.s_axis_cq_tuser(axis_cq_tuser),
|
||||||
|
.s_axis_cq_tvalid(axis_cq_tvalid),
|
||||||
|
|
||||||
|
.m_axis_cc_tdata(axis_cc_tdata),
|
||||||
|
.m_axis_cc_tkeep(axis_cc_tkeep),
|
||||||
|
.m_axis_cc_tlast(axis_cc_tlast),
|
||||||
|
.m_axis_cc_tready(axis_cc_tready),
|
||||||
|
.m_axis_cc_tuser(axis_cc_tuser),
|
||||||
|
.m_axis_cc_tvalid(axis_cc_tvalid),
|
||||||
|
|
||||||
|
.cfg_max_payload(cfg_max_payload),
|
||||||
|
.cfg_max_read_req(cfg_max_read_req),
|
||||||
|
|
||||||
|
.cfg_mgmt_addr(cfg_mgmt_addr),
|
||||||
|
.cfg_mgmt_write(cfg_mgmt_write),
|
||||||
|
.cfg_mgmt_write_data(cfg_mgmt_write_data),
|
||||||
|
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
|
||||||
|
.cfg_mgmt_read(cfg_mgmt_read),
|
||||||
|
.cfg_mgmt_read_data(cfg_mgmt_read_data),
|
||||||
|
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
|
||||||
|
|
||||||
|
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
|
||||||
|
.cfg_interrupt_msi_vf_enable(cfg_interrupt_msi_vf_enable),
|
||||||
|
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
|
||||||
|
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
|
||||||
|
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
|
||||||
|
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
|
||||||
|
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
|
||||||
|
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
|
||||||
|
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
|
||||||
|
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
|
||||||
|
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
|
||||||
|
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
|
||||||
|
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
|
||||||
|
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
|
||||||
|
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
|
||||||
|
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
|
||||||
|
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
|
||||||
|
|
||||||
|
.status_error_cor(status_error_cor),
|
||||||
|
.status_error_uncor(status_error_uncor)
|
||||||
|
);
|
||||||
|
|
||||||
|
endmodule
|
||||||
1089
example/ExaNIC_X10/fpga/rtl/fpga_core.v
Normal file
1089
example/ExaNIC_X10/fpga/rtl/fpga_core.v
Normal file
File diff suppressed because it is too large
Load Diff
52
example/ExaNIC_X10/fpga/rtl/sync_reset.v
Normal file
52
example/ExaNIC_X10/fpga/rtl/sync_reset.v
Normal file
@ -0,0 +1,52 @@
|
|||||||
|
/*
|
||||||
|
|
||||||
|
Copyright (c) 2014-2018 Alex Forencich
|
||||||
|
|
||||||
|
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||||
|
of this software and associated documentation files (the "Software"), to deal
|
||||||
|
in the Software without restriction, including without limitation the rights
|
||||||
|
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||||
|
copies of the Software, and to permit persons to whom the Software is
|
||||||
|
furnished to do so, subject to the following conditions:
|
||||||
|
|
||||||
|
The above copyright notice and this permission notice shall be included in
|
||||||
|
all copies or substantial portions of the Software.
|
||||||
|
|
||||||
|
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||||
|
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||||
|
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||||
|
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||||
|
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||||
|
THE SOFTWARE.
|
||||||
|
|
||||||
|
*/
|
||||||
|
|
||||||
|
// Language: Verilog-2001
|
||||||
|
|
||||||
|
`timescale 1 ns / 1 ps
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Synchronizes an active-high asynchronous reset signal to a given clock by
|
||||||
|
* using a pipeline of N registers.
|
||||||
|
*/
|
||||||
|
module sync_reset #(
|
||||||
|
parameter N=2 // depth of synchronizer
|
||||||
|
)(
|
||||||
|
input wire clk,
|
||||||
|
input wire rst,
|
||||||
|
output wire sync_reset_out
|
||||||
|
);
|
||||||
|
|
||||||
|
reg [N-1:0] sync_reg = {N{1'b1}};
|
||||||
|
|
||||||
|
assign sync_reset_out = sync_reg[N-1];
|
||||||
|
|
||||||
|
always @(posedge clk or posedge rst) begin
|
||||||
|
if (rst)
|
||||||
|
sync_reg <= {N{1'b1}};
|
||||||
|
else
|
||||||
|
sync_reg <= {sync_reg[N-2:0], 1'b0};
|
||||||
|
end
|
||||||
|
|
||||||
|
endmodule
|
||||||
58
example/ExaNIC_X10/fpga/rtl/sync_signal.v
Normal file
58
example/ExaNIC_X10/fpga/rtl/sync_signal.v
Normal file
@ -0,0 +1,58 @@
|
|||||||
|
/*
|
||||||
|
|
||||||
|
Copyright (c) 2014-2018 Alex Forencich
|
||||||
|
|
||||||
|
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||||
|
of this software and associated documentation files (the "Software"), to deal
|
||||||
|
in the Software without restriction, including without limitation the rights
|
||||||
|
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||||
|
copies of the Software, and to permit persons to whom the Software is
|
||||||
|
furnished to do so, subject to the following conditions:
|
||||||
|
|
||||||
|
The above copyright notice and this permission notice shall be included in
|
||||||
|
all copies or substantial portions of the Software.
|
||||||
|
|
||||||
|
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||||
|
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||||
|
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||||
|
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||||
|
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||||
|
THE SOFTWARE.
|
||||||
|
|
||||||
|
*/
|
||||||
|
|
||||||
|
// Language: Verilog-2001
|
||||||
|
|
||||||
|
`timescale 1 ns / 1 ps
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Synchronizes an asyncronous signal to a given clock by using a pipeline of
|
||||||
|
* two registers.
|
||||||
|
*/
|
||||||
|
module sync_signal #(
|
||||||
|
parameter WIDTH=1, // width of the input and output signals
|
||||||
|
parameter N=2 // depth of synchronizer
|
||||||
|
)(
|
||||||
|
input wire clk,
|
||||||
|
input wire [WIDTH-1:0] in,
|
||||||
|
output wire [WIDTH-1:0] out
|
||||||
|
);
|
||||||
|
|
||||||
|
reg [WIDTH-1:0] sync_reg[N-1:0];
|
||||||
|
|
||||||
|
/*
|
||||||
|
* The synchronized output is the last register in the pipeline.
|
||||||
|
*/
|
||||||
|
assign out = sync_reg[N-1];
|
||||||
|
|
||||||
|
integer k;
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
sync_reg[0] <= in;
|
||||||
|
for (k = 1; k < N; k = k + 1) begin
|
||||||
|
sync_reg[k] <= sync_reg[k-1];
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
endmodule
|
||||||
1
example/ExaNIC_X10/fpga/tb/axis_ep.py
Symbolic link
1
example/ExaNIC_X10/fpga/tb/axis_ep.py
Symbolic link
@ -0,0 +1 @@
|
|||||||
|
../lib/pcie/tb/axis_ep.py
|
||||||
1
example/ExaNIC_X10/fpga/tb/pcie.py
Symbolic link
1
example/ExaNIC_X10/fpga/tb/pcie.py
Symbolic link
@ -0,0 +1 @@
|
|||||||
|
../lib/pcie/tb/pcie.py
|
||||||
1
example/ExaNIC_X10/fpga/tb/pcie_us.py
Symbolic link
1
example/ExaNIC_X10/fpga/tb/pcie_us.py
Symbolic link
@ -0,0 +1 @@
|
|||||||
|
../lib/pcie/tb/pcie_us.py
|
||||||
507
example/ExaNIC_X10/fpga/tb/test_fpga_core.py
Executable file
507
example/ExaNIC_X10/fpga/tb/test_fpga_core.py
Executable file
@ -0,0 +1,507 @@
|
|||||||
|
#!/usr/bin/env python
|
||||||
|
"""
|
||||||
|
|
||||||
|
Copyright (c) 2018 Alex Forencich
|
||||||
|
|
||||||
|
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||||
|
of this software and associated documentation files (the "Software"), to deal
|
||||||
|
in the Software without restriction, including without limitation the rights
|
||||||
|
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||||
|
copies of the Software, and to permit persons to whom the Software is
|
||||||
|
furnished to do so, subject to the following conditions:
|
||||||
|
|
||||||
|
The above copyright notice and this permission notice shall be included in
|
||||||
|
all copies or substantial portions of the Software.
|
||||||
|
|
||||||
|
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||||
|
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||||
|
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||||
|
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||||
|
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||||
|
THE SOFTWARE.
|
||||||
|
|
||||||
|
"""
|
||||||
|
|
||||||
|
from myhdl import *
|
||||||
|
import os
|
||||||
|
import struct
|
||||||
|
|
||||||
|
import pcie
|
||||||
|
import pcie_us
|
||||||
|
|
||||||
|
module = 'fpga_core'
|
||||||
|
testbench = 'test_%s' % module
|
||||||
|
|
||||||
|
srcs = []
|
||||||
|
|
||||||
|
srcs.append("../rtl/%s.v" % module)
|
||||||
|
srcs.append("../rtl/axi_ram.v")
|
||||||
|
srcs.append("../rtl/axis_register.v")
|
||||||
|
srcs.append("../lib/pcie/rtl/axis_arb_mux.v")
|
||||||
|
srcs.append("../lib/pcie/rtl/pcie_us_axil_master.v")
|
||||||
|
srcs.append("../lib/pcie/rtl/pcie_us_axi_dma.v")
|
||||||
|
srcs.append("../lib/pcie/rtl/pcie_us_axi_dma_rd.v")
|
||||||
|
srcs.append("../lib/pcie/rtl/pcie_us_axi_dma_wr.v")
|
||||||
|
srcs.append("../lib/pcie/rtl/pcie_tag_manager.v")
|
||||||
|
srcs.append("../lib/pcie/rtl/pcie_us_axi_master.v")
|
||||||
|
srcs.append("../lib/pcie/rtl/pcie_us_axi_master_rd.v")
|
||||||
|
srcs.append("../lib/pcie/rtl/pcie_us_axi_master_wr.v")
|
||||||
|
srcs.append("../lib/pcie/rtl/pcie_us_axis_cq_demux.v")
|
||||||
|
srcs.append("../lib/pcie/rtl/pcie_us_cfg.v")
|
||||||
|
srcs.append("../lib/pcie/rtl/pcie_us_msi.v")
|
||||||
|
srcs.append("../lib/pcie/rtl/arbiter.v")
|
||||||
|
srcs.append("../lib/pcie/rtl/priority_encoder.v")
|
||||||
|
srcs.append("../lib/pcie/rtl/pulse_merge.v")
|
||||||
|
srcs.append("%s.v" % testbench)
|
||||||
|
|
||||||
|
src = ' '.join(srcs)
|
||||||
|
|
||||||
|
build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
|
||||||
|
|
||||||
|
def bench():
|
||||||
|
|
||||||
|
# Parameters
|
||||||
|
|
||||||
|
|
||||||
|
# Inputs
|
||||||
|
clk = Signal(bool(0))
|
||||||
|
rst = Signal(bool(0))
|
||||||
|
current_test = Signal(intbv(0)[8:])
|
||||||
|
|
||||||
|
m_axis_rq_tready = Signal(bool(0))
|
||||||
|
s_axis_rc_tdata = Signal(intbv(0)[256:])
|
||||||
|
s_axis_rc_tkeep = Signal(intbv(0)[8:])
|
||||||
|
s_axis_rc_tlast = Signal(bool(0))
|
||||||
|
s_axis_rc_tuser = Signal(intbv(0)[75:])
|
||||||
|
s_axis_rc_tvalid = Signal(bool(0))
|
||||||
|
s_axis_cq_tdata = Signal(intbv(0)[256:])
|
||||||
|
s_axis_cq_tkeep = Signal(intbv(0)[8:])
|
||||||
|
s_axis_cq_tlast = Signal(bool(0))
|
||||||
|
s_axis_cq_tuser = Signal(intbv(0)[85:])
|
||||||
|
s_axis_cq_tvalid = Signal(bool(0))
|
||||||
|
m_axis_cc_tready = Signal(bool(0))
|
||||||
|
cfg_max_payload = Signal(intbv(0)[3:])
|
||||||
|
cfg_max_read_req = Signal(intbv(0)[3:])
|
||||||
|
cfg_mgmt_read_data = Signal(intbv(0)[32:])
|
||||||
|
cfg_mgmt_read_write_done = Signal(bool(0))
|
||||||
|
cfg_interrupt_msi_enable = Signal(intbv(0)[4:])
|
||||||
|
cfg_interrupt_msi_vf_enable = Signal(intbv(0)[8:])
|
||||||
|
cfg_interrupt_msi_mmenable = Signal(intbv(0)[12:])
|
||||||
|
cfg_interrupt_msi_mask_update = Signal(bool(0))
|
||||||
|
cfg_interrupt_msi_data = Signal(intbv(0)[32:])
|
||||||
|
cfg_interrupt_msi_sent = Signal(bool(0))
|
||||||
|
cfg_interrupt_msi_fail = Signal(bool(0))
|
||||||
|
|
||||||
|
# Outputs
|
||||||
|
sfp_1_led = Signal(intbv(0)[2:])
|
||||||
|
sfp_2_led = Signal(intbv(0)[2:])
|
||||||
|
sma_led = Signal(intbv(0)[2:])
|
||||||
|
m_axis_rq_tdata = Signal(intbv(0)[256:])
|
||||||
|
m_axis_rq_tkeep = Signal(intbv(0)[8:])
|
||||||
|
m_axis_rq_tlast = Signal(bool(0))
|
||||||
|
m_axis_rq_tuser = Signal(intbv(0)[60:])
|
||||||
|
m_axis_rq_tvalid = Signal(bool(0))
|
||||||
|
s_axis_rc_tready = Signal(bool(0))
|
||||||
|
s_axis_cq_tready = Signal(bool(0))
|
||||||
|
m_axis_cc_tdata = Signal(intbv(0)[256:])
|
||||||
|
m_axis_cc_tkeep = Signal(intbv(0)[8:])
|
||||||
|
m_axis_cc_tlast = Signal(bool(0))
|
||||||
|
m_axis_cc_tuser = Signal(intbv(0)[33:])
|
||||||
|
m_axis_cc_tvalid = Signal(bool(0))
|
||||||
|
status_error_cor = Signal(bool(0))
|
||||||
|
status_error_uncor = Signal(bool(0))
|
||||||
|
cfg_mgmt_addr = Signal(intbv(0)[19:])
|
||||||
|
cfg_mgmt_write = Signal(bool(0))
|
||||||
|
cfg_mgmt_write_data = Signal(intbv(0)[32:])
|
||||||
|
cfg_mgmt_byte_enable = Signal(intbv(0)[4:])
|
||||||
|
cfg_mgmt_read = Signal(bool(0))
|
||||||
|
cfg_interrupt_msi_int = Signal(intbv(0)[32:])
|
||||||
|
cfg_interrupt_msi_pending_status = Signal(intbv(0)[32:])
|
||||||
|
cfg_interrupt_msi_select = Signal(intbv(0)[4:])
|
||||||
|
cfg_interrupt_msi_pending_status_function_num = Signal(intbv(0)[4:])
|
||||||
|
cfg_interrupt_msi_pending_status_data_enable = Signal(bool(0))
|
||||||
|
cfg_interrupt_msi_attr = Signal(intbv(0)[3:])
|
||||||
|
cfg_interrupt_msi_tph_present = Signal(bool(0))
|
||||||
|
cfg_interrupt_msi_tph_type = Signal(intbv(0)[2:])
|
||||||
|
cfg_interrupt_msi_tph_st_tag = Signal(intbv(0)[9:])
|
||||||
|
cfg_interrupt_msi_function_number = Signal(intbv(0)[4:])
|
||||||
|
|
||||||
|
# Clock and Reset Interface
|
||||||
|
user_clk=Signal(bool(0))
|
||||||
|
user_reset=Signal(bool(0))
|
||||||
|
sys_clk=Signal(bool(0))
|
||||||
|
sys_reset=Signal(bool(0))
|
||||||
|
|
||||||
|
# PCIe devices
|
||||||
|
rc = pcie.RootComplex()
|
||||||
|
|
||||||
|
mem_base, mem_data = rc.alloc_region(16*1024*1024)
|
||||||
|
|
||||||
|
dev = pcie_us.UltrascalePCIe()
|
||||||
|
|
||||||
|
dev.pcie_generation = 3
|
||||||
|
dev.pcie_link_width = 8
|
||||||
|
dev.user_clock_frequency = 256e6
|
||||||
|
|
||||||
|
dev.functions[0].msi_multiple_message_capable = 5
|
||||||
|
|
||||||
|
dev.functions[0].configure_bar(0, 4*1024*1024)
|
||||||
|
dev.functions[0].configure_bar(1, 4*1024*1024)
|
||||||
|
|
||||||
|
rc.make_port().connect(dev)
|
||||||
|
|
||||||
|
pcie_logic = dev.create_logic(
|
||||||
|
# Completer reQuest Interface
|
||||||
|
m_axis_cq_tdata=s_axis_cq_tdata,
|
||||||
|
m_axis_cq_tuser=s_axis_cq_tuser,
|
||||||
|
m_axis_cq_tlast=s_axis_cq_tlast,
|
||||||
|
m_axis_cq_tkeep=s_axis_cq_tkeep,
|
||||||
|
m_axis_cq_tvalid=s_axis_cq_tvalid,
|
||||||
|
m_axis_cq_tready=s_axis_cq_tready,
|
||||||
|
#pcie_cq_np_req=pcie_cq_np_req,
|
||||||
|
pcie_cq_np_req=Signal(bool(1)),
|
||||||
|
#pcie_cq_np_req_count=pcie_cq_np_req_count,
|
||||||
|
|
||||||
|
# Completer Completion Interface
|
||||||
|
s_axis_cc_tdata=m_axis_cc_tdata,
|
||||||
|
s_axis_cc_tuser=m_axis_cc_tuser,
|
||||||
|
s_axis_cc_tlast=m_axis_cc_tlast,
|
||||||
|
s_axis_cc_tkeep=m_axis_cc_tkeep,
|
||||||
|
s_axis_cc_tvalid=m_axis_cc_tvalid,
|
||||||
|
s_axis_cc_tready=m_axis_cc_tready,
|
||||||
|
|
||||||
|
# Requester reQuest Interface
|
||||||
|
s_axis_rq_tdata=m_axis_rq_tdata,
|
||||||
|
s_axis_rq_tuser=m_axis_rq_tuser,
|
||||||
|
s_axis_rq_tlast=m_axis_rq_tlast,
|
||||||
|
s_axis_rq_tkeep=m_axis_rq_tkeep,
|
||||||
|
s_axis_rq_tvalid=m_axis_rq_tvalid,
|
||||||
|
s_axis_rq_tready=m_axis_rq_tready,
|
||||||
|
#pcie_rq_seq_num=pcie_rq_seq_num,
|
||||||
|
#pcie_rq_seq_num_vld=pcie_rq_seq_num_vld,
|
||||||
|
#pcie_rq_tag=pcie_rq_tag,
|
||||||
|
#pcie_rq_tag_vld=pcie_rq_tag_vld,
|
||||||
|
|
||||||
|
# Requester Completion Interface
|
||||||
|
m_axis_rc_tdata=s_axis_rc_tdata,
|
||||||
|
m_axis_rc_tuser=s_axis_rc_tuser,
|
||||||
|
m_axis_rc_tlast=s_axis_rc_tlast,
|
||||||
|
m_axis_rc_tkeep=s_axis_rc_tkeep,
|
||||||
|
m_axis_rc_tvalid=s_axis_rc_tvalid,
|
||||||
|
m_axis_rc_tready=s_axis_rc_tready,
|
||||||
|
|
||||||
|
# Transmit Flow Control Interface
|
||||||
|
#pcie_tfc_nph_av=pcie_tfc_nph_av,
|
||||||
|
#pcie_tfc_npd_av=pcie_tfc_npd_av,
|
||||||
|
|
||||||
|
# Configuration Management Interface
|
||||||
|
cfg_mgmt_addr=cfg_mgmt_addr,
|
||||||
|
cfg_mgmt_write=cfg_mgmt_write,
|
||||||
|
cfg_mgmt_write_data=cfg_mgmt_write_data,
|
||||||
|
cfg_mgmt_byte_enable=cfg_mgmt_byte_enable,
|
||||||
|
cfg_mgmt_read=cfg_mgmt_read,
|
||||||
|
cfg_mgmt_read_data=cfg_mgmt_read_data,
|
||||||
|
cfg_mgmt_read_write_done=cfg_mgmt_read_write_done,
|
||||||
|
#cfg_mgmt_type1_cfg_reg_access=cfg_mgmt_type1_cfg_reg_access,
|
||||||
|
|
||||||
|
# Configuration Status Interface
|
||||||
|
#cfg_phy_link_down=cfg_phy_link_down,
|
||||||
|
#cfg_phy_link_status=cfg_phy_link_status,
|
||||||
|
#cfg_negotiated_width=cfg_negotiated_width,
|
||||||
|
#cfg_current_speed=cfg_current_speed,
|
||||||
|
cfg_max_payload=cfg_max_payload,
|
||||||
|
cfg_max_read_req=cfg_max_read_req,
|
||||||
|
#cfg_function_status=cfg_function_status,
|
||||||
|
#cfg_vf_status=cfg_vf_status,
|
||||||
|
#cfg_function_power_state=cfg_function_power_state,
|
||||||
|
#cfg_vf_power_state=cfg_vf_power_state,
|
||||||
|
#cfg_link_power_state=cfg_link_power_state,
|
||||||
|
#cfg_err_cor_out=cfg_err_cor_out,
|
||||||
|
#cfg_err_nonfatal_out=cfg_err_nonfatal_out,
|
||||||
|
#cfg_err_fatal_out=cfg_err_fatal_out,
|
||||||
|
#cfg_ltr_enable=cfg_ltr_enable,
|
||||||
|
#cfg_ltssm_state=cfg_ltssm_state,
|
||||||
|
#cfg_rcb_status=cfg_rcb_status,
|
||||||
|
#cfg_dpa_substate_change=cfg_dpa_substate_change,
|
||||||
|
#cfg_obff_enable=cfg_obff_enable,
|
||||||
|
#cfg_pl_status_change=cfg_pl_status_change,
|
||||||
|
#cfg_tph_requester_enable=cfg_tph_requester_enable,
|
||||||
|
#cfg_tph_st_mode=cfg_tph_st_mode,
|
||||||
|
#cfg_vf_tph_requester_enable=cfg_vf_tph_requester_enable,
|
||||||
|
#cfg_vf_tph_st_mode=cfg_vf_tph_st_mode,
|
||||||
|
|
||||||
|
# Configuration Received Message Interface
|
||||||
|
#cfg_msg_received=cfg_msg_received,
|
||||||
|
#cfg_msg_received_data=cfg_msg_received_data,
|
||||||
|
#cfg_msg_received_type=cfg_msg_received_type,
|
||||||
|
|
||||||
|
# Configuration Transmit Message Interface
|
||||||
|
#cfg_msg_transmit=cfg_msg_transmit,
|
||||||
|
#cfg_msg_transmit_type=cfg_msg_transmit_type,
|
||||||
|
#cfg_msg_transmit_data=cfg_msg_transmit_data,
|
||||||
|
#cfg_msg_transmit_done=cfg_msg_transmit_done,
|
||||||
|
|
||||||
|
# Configuration Flow Control Interface
|
||||||
|
#cfg_fc_ph=cfg_fc_ph,
|
||||||
|
#cfg_fc_pd=cfg_fc_pd,
|
||||||
|
#cfg_fc_nph=cfg_fc_nph,
|
||||||
|
#cfg_fc_npd=cfg_fc_npd,
|
||||||
|
#cfg_fc_cplh=cfg_fc_cplh,
|
||||||
|
#cfg_fc_cpld=cfg_fc_cpld,
|
||||||
|
#cfg_fc_sel=cfg_fc_sel,
|
||||||
|
|
||||||
|
# Per-Function Status Interface
|
||||||
|
#cfg_per_func_status_control=cfg_per_func_status_control,
|
||||||
|
#cfg_per_func_status_data=cfg_per_func_status_data,
|
||||||
|
|
||||||
|
# Configuration Control Interface
|
||||||
|
#cfg_hot_reset_in=cfg_hot_reset_in,
|
||||||
|
#cfg_hot_reset_out=cfg_hot_reset_out,
|
||||||
|
#cfg_config_space_enable=cfg_config_space_enable,
|
||||||
|
#cfg_per_function_update_done=cfg_per_function_update_done,
|
||||||
|
#cfg_per_function_number=cfg_per_function_number,
|
||||||
|
#cfg_per_function_output_request=cfg_per_function_output_request,
|
||||||
|
#cfg_dsn=cfg_dsn,
|
||||||
|
#cfg_ds_bus_number=cfg_ds_bus_number,
|
||||||
|
#cfg_ds_device_number=cfg_ds_device_number,
|
||||||
|
#cfg_ds_function_number=cfg_ds_function_number,
|
||||||
|
#cfg_power_state_change_ack=cfg_power_state_change_ack,
|
||||||
|
#cfg_power_state_change_interrupt=cfg_power_state_change_interrupt,
|
||||||
|
cfg_err_cor_in=status_error_cor,
|
||||||
|
cfg_err_uncor_in=status_error_uncor,
|
||||||
|
#cfg_flr_done=cfg_flr_done,
|
||||||
|
#cfg_vf_flr_done=cfg_vf_flr_done,
|
||||||
|
#cfg_flr_in_process=cfg_flr_in_process,
|
||||||
|
#cfg_vf_flr_in_process=cfg_vf_flr_in_process,
|
||||||
|
#cfg_req_pm_transition_l23_ready=cfg_req_pm_transition_l23_ready,
|
||||||
|
#cfg_link_training_enable=cfg_link_training_enable,
|
||||||
|
|
||||||
|
# Configuration Interrupt Controller Interface
|
||||||
|
#cfg_interrupt_int=cfg_interrupt_int,
|
||||||
|
#cfg_interrupt_sent=cfg_interrupt_sent,
|
||||||
|
#cfg_interrupt_pending=cfg_interrupt_pending,
|
||||||
|
cfg_interrupt_msi_enable=cfg_interrupt_msi_enable,
|
||||||
|
cfg_interrupt_msi_vf_enable=cfg_interrupt_msi_vf_enable,
|
||||||
|
cfg_interrupt_msi_mmenable=cfg_interrupt_msi_mmenable,
|
||||||
|
cfg_interrupt_msi_mask_update=cfg_interrupt_msi_mask_update,
|
||||||
|
cfg_interrupt_msi_data=cfg_interrupt_msi_data,
|
||||||
|
cfg_interrupt_msi_select=cfg_interrupt_msi_select,
|
||||||
|
cfg_interrupt_msi_int=cfg_interrupt_msi_int,
|
||||||
|
cfg_interrupt_msi_pending_status=cfg_interrupt_msi_pending_status,
|
||||||
|
cfg_interrupt_msi_pending_status_data_enable=cfg_interrupt_msi_pending_status_data_enable,
|
||||||
|
cfg_interrupt_msi_pending_status_function_num=cfg_interrupt_msi_pending_status_function_num,
|
||||||
|
cfg_interrupt_msi_sent=cfg_interrupt_msi_sent,
|
||||||
|
cfg_interrupt_msi_fail=cfg_interrupt_msi_fail,
|
||||||
|
#cfg_interrupt_msix_enable=cfg_interrupt_msix_enable,
|
||||||
|
#cfg_interrupt_msix_mask=cfg_interrupt_msix_mask,
|
||||||
|
#cfg_interrupt_msix_vf_enable=cfg_interrupt_msix_vf_enable,
|
||||||
|
#cfg_interrupt_msix_vf_mask=cfg_interrupt_msix_vf_mask,
|
||||||
|
#cfg_interrupt_msix_address=cfg_interrupt_msix_address,
|
||||||
|
#cfg_interrupt_msix_data=cfg_interrupt_msix_data,
|
||||||
|
#cfg_interrupt_msix_int=cfg_interrupt_msix_int,
|
||||||
|
#cfg_interrupt_msix_sent=cfg_interrupt_msix_sent,
|
||||||
|
#cfg_interrupt_msix_fail=cfg_interrupt_msix_fail,
|
||||||
|
cfg_interrupt_msi_attr=cfg_interrupt_msi_attr,
|
||||||
|
cfg_interrupt_msi_tph_present=cfg_interrupt_msi_tph_present,
|
||||||
|
cfg_interrupt_msi_tph_type=cfg_interrupt_msi_tph_type,
|
||||||
|
cfg_interrupt_msi_tph_st_tag=cfg_interrupt_msi_tph_st_tag,
|
||||||
|
cfg_interrupt_msi_function_number=cfg_interrupt_msi_function_number,
|
||||||
|
|
||||||
|
# Configuration Extend Interface
|
||||||
|
#cfg_ext_read_received=cfg_ext_read_received,
|
||||||
|
#cfg_ext_write_received=cfg_ext_write_received,
|
||||||
|
#cfg_ext_register_number=cfg_ext_register_number,
|
||||||
|
#cfg_ext_function_number=cfg_ext_function_number,
|
||||||
|
#cfg_ext_write_data=cfg_ext_write_data,
|
||||||
|
#cfg_ext_write_byte_enable=cfg_ext_write_byte_enable,
|
||||||
|
#cfg_ext_read_data=cfg_ext_read_data,
|
||||||
|
#cfg_ext_read_data_valid=cfg_ext_read_data_valid,
|
||||||
|
|
||||||
|
# Clock and Reset Interface
|
||||||
|
user_clk=user_clk,
|
||||||
|
user_reset=user_reset,
|
||||||
|
sys_clk=sys_clk,
|
||||||
|
sys_clk_gt=sys_clk,
|
||||||
|
sys_reset=sys_reset,
|
||||||
|
#pcie_perstn0_out=pcie_perstn0_out,
|
||||||
|
#pcie_perstn1_in=pcie_perstn1_in,
|
||||||
|
#pcie_perstn1_out=pcie_perstn1_out
|
||||||
|
)
|
||||||
|
|
||||||
|
# DUT
|
||||||
|
if os.system(build_cmd):
|
||||||
|
raise Exception("Error running build command")
|
||||||
|
|
||||||
|
dut = Cosimulation(
|
||||||
|
"vvp -m myhdl %s.vvp -lxt2" % testbench,
|
||||||
|
clk=user_clk,
|
||||||
|
rst=user_reset,
|
||||||
|
current_test=current_test,
|
||||||
|
sfp_1_led=sfp_1_led,
|
||||||
|
sfp_2_led=sfp_2_led,
|
||||||
|
sma_led=sma_led,
|
||||||
|
m_axis_rq_tdata=m_axis_rq_tdata,
|
||||||
|
m_axis_rq_tkeep=m_axis_rq_tkeep,
|
||||||
|
m_axis_rq_tlast=m_axis_rq_tlast,
|
||||||
|
m_axis_rq_tready=m_axis_rq_tready,
|
||||||
|
m_axis_rq_tuser=m_axis_rq_tuser,
|
||||||
|
m_axis_rq_tvalid=m_axis_rq_tvalid,
|
||||||
|
s_axis_rc_tdata=s_axis_rc_tdata,
|
||||||
|
s_axis_rc_tkeep=s_axis_rc_tkeep,
|
||||||
|
s_axis_rc_tlast=s_axis_rc_tlast,
|
||||||
|
s_axis_rc_tready=s_axis_rc_tready,
|
||||||
|
s_axis_rc_tuser=s_axis_rc_tuser,
|
||||||
|
s_axis_rc_tvalid=s_axis_rc_tvalid,
|
||||||
|
s_axis_cq_tdata=s_axis_cq_tdata,
|
||||||
|
s_axis_cq_tkeep=s_axis_cq_tkeep,
|
||||||
|
s_axis_cq_tlast=s_axis_cq_tlast,
|
||||||
|
s_axis_cq_tready=s_axis_cq_tready,
|
||||||
|
s_axis_cq_tuser=s_axis_cq_tuser,
|
||||||
|
s_axis_cq_tvalid=s_axis_cq_tvalid,
|
||||||
|
m_axis_cc_tdata=m_axis_cc_tdata,
|
||||||
|
m_axis_cc_tkeep=m_axis_cc_tkeep,
|
||||||
|
m_axis_cc_tlast=m_axis_cc_tlast,
|
||||||
|
m_axis_cc_tready=m_axis_cc_tready,
|
||||||
|
m_axis_cc_tuser=m_axis_cc_tuser,
|
||||||
|
m_axis_cc_tvalid=m_axis_cc_tvalid,
|
||||||
|
cfg_max_payload=cfg_max_payload,
|
||||||
|
cfg_max_read_req=cfg_max_read_req,
|
||||||
|
cfg_mgmt_addr=cfg_mgmt_addr,
|
||||||
|
cfg_mgmt_write=cfg_mgmt_write,
|
||||||
|
cfg_mgmt_write_data=cfg_mgmt_write_data,
|
||||||
|
cfg_mgmt_byte_enable=cfg_mgmt_byte_enable,
|
||||||
|
cfg_mgmt_read=cfg_mgmt_read,
|
||||||
|
cfg_mgmt_read_data=cfg_mgmt_read_data,
|
||||||
|
cfg_mgmt_read_write_done=cfg_mgmt_read_write_done,
|
||||||
|
cfg_interrupt_msi_enable=cfg_interrupt_msi_enable,
|
||||||
|
cfg_interrupt_msi_vf_enable=cfg_interrupt_msi_vf_enable,
|
||||||
|
cfg_interrupt_msi_int=cfg_interrupt_msi_int,
|
||||||
|
cfg_interrupt_msi_sent=cfg_interrupt_msi_sent,
|
||||||
|
cfg_interrupt_msi_fail=cfg_interrupt_msi_fail,
|
||||||
|
cfg_interrupt_msi_mmenable=cfg_interrupt_msi_mmenable,
|
||||||
|
cfg_interrupt_msi_pending_status=cfg_interrupt_msi_pending_status,
|
||||||
|
cfg_interrupt_msi_mask_update=cfg_interrupt_msi_mask_update,
|
||||||
|
cfg_interrupt_msi_select=cfg_interrupt_msi_select,
|
||||||
|
cfg_interrupt_msi_data=cfg_interrupt_msi_data,
|
||||||
|
cfg_interrupt_msi_pending_status_function_num=cfg_interrupt_msi_pending_status_function_num,
|
||||||
|
cfg_interrupt_msi_pending_status_data_enable=cfg_interrupt_msi_pending_status_data_enable,
|
||||||
|
cfg_interrupt_msi_attr=cfg_interrupt_msi_attr,
|
||||||
|
cfg_interrupt_msi_tph_present=cfg_interrupt_msi_tph_present,
|
||||||
|
cfg_interrupt_msi_tph_type=cfg_interrupt_msi_tph_type,
|
||||||
|
cfg_interrupt_msi_tph_st_tag=cfg_interrupt_msi_tph_st_tag,
|
||||||
|
cfg_interrupt_msi_function_number=cfg_interrupt_msi_function_number,
|
||||||
|
status_error_cor=status_error_cor,
|
||||||
|
status_error_uncor=status_error_uncor
|
||||||
|
)
|
||||||
|
|
||||||
|
@always(delay(5))
|
||||||
|
def clkgen():
|
||||||
|
clk.next = not clk
|
||||||
|
|
||||||
|
@always_comb
|
||||||
|
def clk_logic():
|
||||||
|
sys_clk.next = clk
|
||||||
|
sys_reset.next = not rst
|
||||||
|
|
||||||
|
@instance
|
||||||
|
def check():
|
||||||
|
yield delay(100)
|
||||||
|
yield clk.posedge
|
||||||
|
rst.next = 1
|
||||||
|
yield clk.posedge
|
||||||
|
rst.next = 0
|
||||||
|
yield clk.posedge
|
||||||
|
yield delay(100)
|
||||||
|
yield clk.posedge
|
||||||
|
|
||||||
|
# testbench stimulus
|
||||||
|
|
||||||
|
current_tag = 1
|
||||||
|
|
||||||
|
yield clk.posedge
|
||||||
|
print("test 1: enumeration")
|
||||||
|
current_test.next = 1
|
||||||
|
|
||||||
|
yield rc.enumerate(enable_bus_mastering=True, configure_msi=True)
|
||||||
|
|
||||||
|
dev_pf0_bar0 = dev.functions[0].bar[0] & 0xfffffffc
|
||||||
|
dev_pf0_bar1 = dev.functions[0].bar[1] & 0xfffffffc
|
||||||
|
|
||||||
|
yield delay(100)
|
||||||
|
|
||||||
|
yield clk.posedge
|
||||||
|
print("test 2: memory write to bar 1")
|
||||||
|
current_test.next = 2
|
||||||
|
|
||||||
|
yield rc.mem_write(dev_pf0_bar1, b'\x11\x22\x33\x44')
|
||||||
|
|
||||||
|
yield delay(100)
|
||||||
|
|
||||||
|
yield clk.posedge
|
||||||
|
print("test 3: memory read from bar 1")
|
||||||
|
current_test.next = 3
|
||||||
|
|
||||||
|
val = yield from rc.mem_read(dev_pf0_bar1, 4, 1000)
|
||||||
|
print(val)
|
||||||
|
assert val == b'\x11\x22\x33\x44'
|
||||||
|
|
||||||
|
yield delay(100)
|
||||||
|
|
||||||
|
yield clk.posedge
|
||||||
|
print("test 4: test DMA")
|
||||||
|
current_test.next = 4
|
||||||
|
|
||||||
|
# write packet data
|
||||||
|
mem_data[0:1024] = bytearray([x%256 for x in range(1024)])
|
||||||
|
|
||||||
|
# enable DMA
|
||||||
|
yield rc.mem_write(dev_pf0_bar0+0x100000, struct.pack('<L', 1))
|
||||||
|
|
||||||
|
# write pcie read descriptor
|
||||||
|
yield rc.mem_write(dev_pf0_bar0+0x100100, struct.pack('<L', (mem_base+0x0000) & 0xffffffff))
|
||||||
|
yield rc.mem_write(dev_pf0_bar0+0x100104, struct.pack('<L', (mem_base+0x0000 >> 32) & 0xffffffff))
|
||||||
|
yield rc.mem_write(dev_pf0_bar0+0x100108, struct.pack('<L', (0x100) & 0xffffffff))
|
||||||
|
yield rc.mem_write(dev_pf0_bar0+0x10010C, struct.pack('<L', (0x100 >> 32) & 0xffffffff))
|
||||||
|
yield rc.mem_write(dev_pf0_bar0+0x100110, struct.pack('<L', 0x400))
|
||||||
|
yield rc.mem_write(dev_pf0_bar0+0x100114, struct.pack('<L', 0xAA))
|
||||||
|
|
||||||
|
yield delay(2000)
|
||||||
|
|
||||||
|
# read status
|
||||||
|
val = yield from rc.mem_read(dev_pf0_bar0+0x100118, 4)
|
||||||
|
print(val)
|
||||||
|
|
||||||
|
# write pcie write descriptor
|
||||||
|
yield rc.mem_write(dev_pf0_bar0+0x100200, struct.pack('<L', (mem_base+0x1000) & 0xffffffff))
|
||||||
|
yield rc.mem_write(dev_pf0_bar0+0x100204, struct.pack('<L', (mem_base+0x1000 >> 32) & 0xffffffff))
|
||||||
|
yield rc.mem_write(dev_pf0_bar0+0x100208, struct.pack('<L', (0x100) & 0xffffffff))
|
||||||
|
yield rc.mem_write(dev_pf0_bar0+0x10020C, struct.pack('<L', (0x100 >> 32) & 0xffffffff))
|
||||||
|
yield rc.mem_write(dev_pf0_bar0+0x100210, struct.pack('<L', 0x400))
|
||||||
|
yield rc.mem_write(dev_pf0_bar0+0x100214, struct.pack('<L', 0x55))
|
||||||
|
|
||||||
|
yield delay(2000)
|
||||||
|
|
||||||
|
# read status
|
||||||
|
val = yield from rc.mem_read(dev_pf0_bar0+0x100218, 4)
|
||||||
|
print(val)
|
||||||
|
|
||||||
|
data = mem_data[0x1000:(0x1000)+64]
|
||||||
|
for i in range(0, len(data), 16):
|
||||||
|
print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
|
||||||
|
|
||||||
|
assert mem_data[0:1024] == mem_data[0x1000:0x1000+1024]
|
||||||
|
|
||||||
|
yield delay(100)
|
||||||
|
|
||||||
|
raise StopSimulation
|
||||||
|
|
||||||
|
return instances()
|
||||||
|
|
||||||
|
def test_bench():
|
||||||
|
sim = Simulation(bench())
|
||||||
|
sim.run()
|
||||||
|
|
||||||
|
if __name__ == '__main__':
|
||||||
|
print("Running test...")
|
||||||
|
test_bench()
|
||||||
230
example/ExaNIC_X10/fpga/tb/test_fpga_core.v
Normal file
230
example/ExaNIC_X10/fpga/tb/test_fpga_core.v
Normal file
@ -0,0 +1,230 @@
|
|||||||
|
/*
|
||||||
|
|
||||||
|
Copyright (c) 2018 Alex Forencich
|
||||||
|
|
||||||
|
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||||
|
of this software and associated documentation files (the "Software"), to deal
|
||||||
|
in the Software without restriction, including without limitation the rights
|
||||||
|
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||||
|
copies of the Software, and to permit persons to whom the Software is
|
||||||
|
furnished to do so, subject to the following conditions:
|
||||||
|
|
||||||
|
The above copyright notice and this permission notice shall be included in
|
||||||
|
all copies or substantial portions of the Software.
|
||||||
|
|
||||||
|
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||||
|
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||||
|
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||||
|
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||||
|
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||||
|
THE SOFTWARE.
|
||||||
|
|
||||||
|
*/
|
||||||
|
|
||||||
|
// Language: Verilog 2001
|
||||||
|
|
||||||
|
`timescale 1ns / 1ps
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Testbench for fpga_core
|
||||||
|
*/
|
||||||
|
module test_fpga_core;
|
||||||
|
|
||||||
|
// Parameters
|
||||||
|
|
||||||
|
// Inputs
|
||||||
|
reg clk = 0;
|
||||||
|
reg rst = 0;
|
||||||
|
reg [7:0] current_test = 0;
|
||||||
|
|
||||||
|
reg m_axis_rq_tready = 0;
|
||||||
|
reg [255:0] s_axis_rc_tdata = 0;
|
||||||
|
reg [7:0] s_axis_rc_tkeep = 0;
|
||||||
|
reg s_axis_rc_tlast = 0;
|
||||||
|
reg [74:0] s_axis_rc_tuser = 0;
|
||||||
|
reg s_axis_rc_tvalid = 0;
|
||||||
|
reg [255:0] s_axis_cq_tdata = 0;
|
||||||
|
reg [7:0] s_axis_cq_tkeep = 0;
|
||||||
|
reg s_axis_cq_tlast = 0;
|
||||||
|
reg [84:0] s_axis_cq_tuser = 0;
|
||||||
|
reg s_axis_cq_tvalid = 0;
|
||||||
|
reg m_axis_cc_tready = 0;
|
||||||
|
reg [2:0] cfg_max_payload = 0;
|
||||||
|
reg [2:0] cfg_max_read_req = 0;
|
||||||
|
reg [31:0] cfg_mgmt_read_data = 0;
|
||||||
|
reg cfg_mgmt_read_write_done = 0;
|
||||||
|
reg [3:0] cfg_interrupt_msi_enable = 0;
|
||||||
|
reg [7:0] cfg_interrupt_msi_vf_enable = 0;
|
||||||
|
reg [11:0] cfg_interrupt_msi_mmenable = 0;
|
||||||
|
reg cfg_interrupt_msi_mask_update = 0;
|
||||||
|
reg [31:0] cfg_interrupt_msi_data = 0;
|
||||||
|
reg cfg_interrupt_msi_sent = 0;
|
||||||
|
reg cfg_interrupt_msi_fail = 0;
|
||||||
|
|
||||||
|
// Outputs
|
||||||
|
wire [1:0] sfp_1_led;
|
||||||
|
wire [1:0] sfp_2_led;
|
||||||
|
wire [1:0] sma_led;
|
||||||
|
wire [255:0] m_axis_rq_tdata;
|
||||||
|
wire [7:0] m_axis_rq_tkeep;
|
||||||
|
wire m_axis_rq_tlast;
|
||||||
|
wire [59:0] m_axis_rq_tuser;
|
||||||
|
wire m_axis_rq_tvalid;
|
||||||
|
wire s_axis_rc_tready;
|
||||||
|
wire s_axis_cq_tready;
|
||||||
|
wire [255:0] m_axis_cc_tdata;
|
||||||
|
wire [7:0] m_axis_cc_tkeep;
|
||||||
|
wire m_axis_cc_tlast;
|
||||||
|
wire [32:0] m_axis_cc_tuser;
|
||||||
|
wire m_axis_cc_tvalid;
|
||||||
|
wire [18:0] cfg_mgmt_addr;
|
||||||
|
wire cfg_mgmt_write;
|
||||||
|
wire [31:0] cfg_mgmt_write_data;
|
||||||
|
wire [3:0] cfg_mgmt_byte_enable;
|
||||||
|
wire cfg_mgmt_read;
|
||||||
|
wire [3:0] cfg_interrupt_msi_select;
|
||||||
|
wire [31:0] cfg_interrupt_msi_int;
|
||||||
|
wire [31:0] cfg_interrupt_msi_pending_status;
|
||||||
|
wire cfg_interrupt_msi_pending_status_data_enable;
|
||||||
|
wire [3:0] cfg_interrupt_msi_pending_status_function_num;
|
||||||
|
wire [2:0] cfg_interrupt_msi_attr;
|
||||||
|
wire cfg_interrupt_msi_tph_present;
|
||||||
|
wire [1:0] cfg_interrupt_msi_tph_type;
|
||||||
|
wire [8:0] cfg_interrupt_msi_tph_st_tag;
|
||||||
|
wire [3:0] cfg_interrupt_msi_function_number;
|
||||||
|
wire status_error_cor;
|
||||||
|
wire status_error_uncor;
|
||||||
|
|
||||||
|
initial begin
|
||||||
|
// myhdl integration
|
||||||
|
$from_myhdl(
|
||||||
|
clk,
|
||||||
|
rst,
|
||||||
|
current_test,
|
||||||
|
m_axis_rq_tready,
|
||||||
|
s_axis_rc_tdata,
|
||||||
|
s_axis_rc_tkeep,
|
||||||
|
s_axis_rc_tlast,
|
||||||
|
s_axis_rc_tuser,
|
||||||
|
s_axis_rc_tvalid,
|
||||||
|
s_axis_cq_tdata,
|
||||||
|
s_axis_cq_tkeep,
|
||||||
|
s_axis_cq_tlast,
|
||||||
|
s_axis_cq_tuser,
|
||||||
|
s_axis_cq_tvalid,
|
||||||
|
m_axis_cc_tready,
|
||||||
|
cfg_max_payload,
|
||||||
|
cfg_max_read_req,
|
||||||
|
cfg_mgmt_read_data,
|
||||||
|
cfg_mgmt_read_write_done,
|
||||||
|
cfg_interrupt_msi_enable,
|
||||||
|
cfg_interrupt_msi_vf_enable,
|
||||||
|
cfg_interrupt_msi_mmenable,
|
||||||
|
cfg_interrupt_msi_mask_update,
|
||||||
|
cfg_interrupt_msi_data,
|
||||||
|
cfg_interrupt_msi_sent,
|
||||||
|
cfg_interrupt_msi_fail
|
||||||
|
);
|
||||||
|
$to_myhdl(
|
||||||
|
sfp_1_led,
|
||||||
|
sfp_2_led,
|
||||||
|
sma_led,
|
||||||
|
m_axis_rq_tdata,
|
||||||
|
m_axis_rq_tkeep,
|
||||||
|
m_axis_rq_tlast,
|
||||||
|
m_axis_rq_tuser,
|
||||||
|
m_axis_rq_tvalid,
|
||||||
|
s_axis_rc_tready,
|
||||||
|
s_axis_cq_tready,
|
||||||
|
m_axis_cc_tdata,
|
||||||
|
m_axis_cc_tkeep,
|
||||||
|
m_axis_cc_tlast,
|
||||||
|
m_axis_cc_tuser,
|
||||||
|
m_axis_cc_tvalid,
|
||||||
|
cfg_mgmt_addr,
|
||||||
|
cfg_mgmt_write,
|
||||||
|
cfg_mgmt_write_data,
|
||||||
|
cfg_mgmt_byte_enable,
|
||||||
|
cfg_mgmt_read,
|
||||||
|
cfg_interrupt_msi_select,
|
||||||
|
cfg_interrupt_msi_int,
|
||||||
|
cfg_interrupt_msi_pending_status,
|
||||||
|
cfg_interrupt_msi_pending_status_data_enable,
|
||||||
|
cfg_interrupt_msi_pending_status_function_num,
|
||||||
|
cfg_interrupt_msi_attr,
|
||||||
|
cfg_interrupt_msi_tph_present,
|
||||||
|
cfg_interrupt_msi_tph_type,
|
||||||
|
cfg_interrupt_msi_tph_st_tag,
|
||||||
|
cfg_interrupt_msi_function_number,
|
||||||
|
status_error_cor,
|
||||||
|
status_error_uncor
|
||||||
|
);
|
||||||
|
|
||||||
|
// dump file
|
||||||
|
$dumpfile("test_fpga_core.lxt");
|
||||||
|
$dumpvars(0, test_fpga_core);
|
||||||
|
end
|
||||||
|
|
||||||
|
fpga_core
|
||||||
|
UUT (
|
||||||
|
.clk(clk),
|
||||||
|
.rst(rst),
|
||||||
|
.sfp_1_led(sfp_1_led),
|
||||||
|
.sfp_2_led(sfp_2_led),
|
||||||
|
.sma_led(sma_led),
|
||||||
|
.m_axis_rq_tdata(m_axis_rq_tdata),
|
||||||
|
.m_axis_rq_tkeep(m_axis_rq_tkeep),
|
||||||
|
.m_axis_rq_tlast(m_axis_rq_tlast),
|
||||||
|
.m_axis_rq_tready(m_axis_rq_tready),
|
||||||
|
.m_axis_rq_tuser(m_axis_rq_tuser),
|
||||||
|
.m_axis_rq_tvalid(m_axis_rq_tvalid),
|
||||||
|
.s_axis_rc_tdata(s_axis_rc_tdata),
|
||||||
|
.s_axis_rc_tkeep(s_axis_rc_tkeep),
|
||||||
|
.s_axis_rc_tlast(s_axis_rc_tlast),
|
||||||
|
.s_axis_rc_tready(s_axis_rc_tready),
|
||||||
|
.s_axis_rc_tuser(s_axis_rc_tuser),
|
||||||
|
.s_axis_rc_tvalid(s_axis_rc_tvalid),
|
||||||
|
.s_axis_cq_tdata(s_axis_cq_tdata),
|
||||||
|
.s_axis_cq_tkeep(s_axis_cq_tkeep),
|
||||||
|
.s_axis_cq_tlast(s_axis_cq_tlast),
|
||||||
|
.s_axis_cq_tready(s_axis_cq_tready),
|
||||||
|
.s_axis_cq_tuser(s_axis_cq_tuser),
|
||||||
|
.s_axis_cq_tvalid(s_axis_cq_tvalid),
|
||||||
|
.m_axis_cc_tdata(m_axis_cc_tdata),
|
||||||
|
.m_axis_cc_tkeep(m_axis_cc_tkeep),
|
||||||
|
.m_axis_cc_tlast(m_axis_cc_tlast),
|
||||||
|
.m_axis_cc_tready(m_axis_cc_tready),
|
||||||
|
.m_axis_cc_tuser(m_axis_cc_tuser),
|
||||||
|
.m_axis_cc_tvalid(m_axis_cc_tvalid),
|
||||||
|
.cfg_max_payload(cfg_max_payload),
|
||||||
|
.cfg_max_read_req(cfg_max_read_req),
|
||||||
|
.cfg_mgmt_addr(cfg_mgmt_addr),
|
||||||
|
.cfg_mgmt_write(cfg_mgmt_write),
|
||||||
|
.cfg_mgmt_write_data(cfg_mgmt_write_data),
|
||||||
|
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
|
||||||
|
.cfg_mgmt_read(cfg_mgmt_read),
|
||||||
|
.cfg_mgmt_read_data(cfg_mgmt_read_data),
|
||||||
|
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
|
||||||
|
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
|
||||||
|
.cfg_interrupt_msi_vf_enable(cfg_interrupt_msi_vf_enable),
|
||||||
|
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
|
||||||
|
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
|
||||||
|
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
|
||||||
|
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
|
||||||
|
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
|
||||||
|
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
|
||||||
|
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
|
||||||
|
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
|
||||||
|
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
|
||||||
|
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
|
||||||
|
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
|
||||||
|
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
|
||||||
|
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
|
||||||
|
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
|
||||||
|
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
|
||||||
|
.status_error_cor(status_error_cor),
|
||||||
|
.status_error_uncor(status_error_uncor)
|
||||||
|
);
|
||||||
|
|
||||||
|
endmodule
|
||||||
Loading…
x
Reference in New Issue
Block a user