FPGA/verilog-pcie
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

Print TLP payloads in hex

Browse Source
This commit is contained in:
Alex Forencich 2019-01-28 18:17:21 -08:00
parent 667b5c42c5
commit 9f36acebc2
2 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
tb/pcie.py
View File

@ -563,7 +563,7 @@ class TLP(object):
def __repr__(self): def __repr__(self):
return ( return (
('TLP(data=%s, ' % repr(self.data)) + ('TLP(data=[%s], ' % ', '.join(hex(x) for x in self.data)) +
('fmt=0x%x, ' % self.fmt) + ('fmt=0x%x, ' % self.fmt) +
('type=0x%x, ' % self.type) + ('type=0x%x, ' % self.type) +
('tc=0x%x, ' % self.tc) + ('tc=0x%x, ' % self.tc) +

2
tb/pcie_us.py
View File

@ -618,7 +618,7 @@ class TLP_us(TLP):
def __repr__(self): def __repr__(self):
return ( return (
('TLP_us(data=%s, ' % repr(self.data)) + ('TLP_us(data=[%s], ' % ', '.join(hex(x) for x in self.data)) +
('fmt=0x%x, ' % self.fmt) + ('fmt=0x%x, ' % self.fmt) +
('type=0x%x, ' % self.type) + ('type=0x%x, ' % self.type) +
('tc=0x%x, ' % self.tc) + ('tc=0x%x, ' % self.tc) +