FPGA/verilog-pcie
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Remove extraneous character

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This commit is contained in:
Alex Forencich 2019-12-07 14:36:32 -08:00
parent d561195dc8
commit a6d64bbcbb
1 changed files with 1 additions and 1 deletions
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tb/test_dma_if_pcie_us_rd_128.py
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@ -53,7 +53,7 @@ def bench():
AXIS_PCIE_RC_USER_WIDTH = 75 AXIS_PCIE_RC_USER_WIDTH = 75
AXIS_PCIE_RQ_USER_WIDTH = 60 AXIS_PCIE_RQ_USER_WIDTH = 60
RQ_SEQ_NUM_WIDTH = 4 if AXIS_PCIE_RQ_USER_WIDTH == 60 else 6 RQ_SEQ_NUM_WIDTH = 4 if AXIS_PCIE_RQ_USER_WIDTH == 60 else 6
RQ_SEQ_NUM_ENABLE = 1c RQ_SEQ_NUM_ENABLE = 1
SEG_COUNT = max(2, int(AXIS_PCIE_DATA_WIDTH*2/128)) SEG_COUNT = max(2, int(AXIS_PCIE_DATA_WIDTH*2/128))
SEG_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH*2/SEG_COUNT SEG_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH*2/SEG_COUNT
SEG_ADDR_WIDTH = 12 SEG_ADDR_WIDTH = 12