FPGA/verilog-pcie
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Fix discontinue masks

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This commit is contained in:
Alex Forencich 2019-11-23 00:20:21 -08:00
parent a77effe885
commit b2c5004962
1 changed files with 2 additions and 2 deletions
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4
tb/pcie_us.py
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@ -1249,7 +1249,7 @@ class RQSource(object):
u |= 0b00 << 22 # is_sop0_ptr
if frame.discontinue:
u |= 36 # discontinue
u |= 1 << 36 # discontinue
last_lane = 0
@ -1271,7 +1271,7 @@ class RQSource(object):
u |= (frame.last_be & 0xf) << 4
if frame.discontinue:
u |= 11 # discontinue
u |= 1 << 11 # discontinue
for i in range(len(tkeep)):
if data: