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Update testbenches

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This commit is contained in:
Alex Forencich 2019-01-02 02:00:46 -08:00
parent 852d583282
commit bb4fa0bfa0
6 changed files with 17 additions and 23 deletions
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6
tb/test_pcie_us_axi_dma_rd_128.py
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@ -441,8 +441,8 @@ def bench():
print("test 3: various reads") print("test 3: various reads")
current_test.next = 3 current_test.next = 3
for length in list(range(1,19))+[1024]: for length in list(range(1,19))+list(range(128-4,128+4))+[1024]:
for pcie_offset in list(range(8,13))+list(range(4096-4,4096)): for pcie_offset in list(range(8,13))+list(range(4096-4,4096+4)):
for axi_offset in list(range(8,25))+list(range(4096-16,4096)): for axi_offset in list(range(8,25))+list(range(4096-16,4096)):
for pause in [False, True]: for pause in [False, True]:
print("length %d, pcie_offset %d, axi_offset %d"% (length, pcie_offset, axi_offset)) print("length %d, pcie_offset %d, axi_offset %d"% (length, pcie_offset, axi_offset))
@ -469,8 +469,6 @@ def bench():
rq_pause_toggle.next = 0 rq_pause_toggle.next = 0
rc_pause_toggle.next = 0 rc_pause_toggle.next = 0
yield delay(100)
status = read_desc_status_sink.recv() status = read_desc_status_sink.recv()
print(status) print(status)

9
tb/test_pcie_us_axi_dma_rd_256.py
View File

@ -441,11 +441,10 @@ def bench():
print("test 3: various reads") print("test 3: various reads")
current_test.next = 3 current_test.next = 3
for length in list(range(1,35))+[1024]: for length in list(range(1,35))+list(range(128-4,128+4))+[1024]:
for pcie_offset in list(range(8,13))+list(range(4096-4,4096)): for pcie_offset in list(range(8,13))+list(range(4096-4,4096+4)):
for axi_offset in list(range(8,41))+list(range(4096-32,4096)): for axi_offset in list(range(8,41))+list(range(4096-32,4096)):
#for pause in [False, True]: for pause in [False, True]:
for pause in [False]:
print("length %d, pcie_offset %d, axi_offset %d"% (length, pcie_offset, axi_offset)) print("length %d, pcie_offset %d, axi_offset %d"% (length, pcie_offset, axi_offset))
#pcie_addr = length * 0x100000000 + pcie_offset * 0x10000 + offset #pcie_addr = length * 0x100000000 + pcie_offset * 0x10000 + offset
pcie_addr = pcie_offset pcie_addr = pcie_offset
@ -470,8 +469,6 @@ def bench():
rq_pause_toggle.next = 0 rq_pause_toggle.next = 0
rc_pause_toggle.next = 0 rc_pause_toggle.next = 0
yield delay(100)
status = read_desc_status_sink.recv() status = read_desc_status_sink.recv()
print(status) print(status)

6
tb/test_pcie_us_axi_dma_rd_64.py
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@ -441,8 +441,8 @@ def bench():
print("test 3: various reads") print("test 3: various reads")
current_test.next = 3 current_test.next = 3
for length in list(range(1,11))+[1024]: for length in list(range(1,11))+list(range(128-4,128+4))+[1024]:
for pcie_offset in list(range(8,13))+list(range(4096-4,4096)): for pcie_offset in list(range(8,13))+list(range(4096-4,4096+4)):
for axi_offset in list(range(8,17))+list(range(4096-8,4096)): for axi_offset in list(range(8,17))+list(range(4096-8,4096)):
for pause in [False, True]: for pause in [False, True]:
print("length %d, pcie_offset %d, axi_offset %d"% (length, pcie_offset, axi_offset)) print("length %d, pcie_offset %d, axi_offset %d"% (length, pcie_offset, axi_offset))
@ -469,8 +469,6 @@ def bench():
rq_pause_toggle.next = 0 rq_pause_toggle.next = 0
rc_pause_toggle.next = 0 rc_pause_toggle.next = 0
yield delay(100)
status = read_desc_status_sink.recv() status = read_desc_status_sink.recv()
print(status) print(status)

6
tb/test_pcie_us_axi_dma_wr_128.py
View File

@ -393,8 +393,8 @@ def bench():
print("test 3: various writes") print("test 3: various writes")
current_test.next = 3 current_test.next = 3
for length in list(range(1,19))+[1024]: for length in list(range(1,19))+list(range(128-4,128+4))+[1024]:
for pcie_offset in list(range(8,13))+list(range(4096-4,4096)): for pcie_offset in list(range(8,13))+list(range(4096-4,4096+4)):
for axi_offset in list(range(8,25))+list(range(4096-16,4096)): for axi_offset in list(range(8,25))+list(range(4096-16,4096)):
for pause in [False, True]: for pause in [False, True]:
print("length %d, pcie_offset %d, axi_offset %d"% (length, pcie_offset, axi_offset)) print("length %d, pcie_offset %d, axi_offset %d"% (length, pcie_offset, axi_offset))
@ -404,7 +404,7 @@ def bench():
test_data = bytearray([x%256 for x in range(length)]) test_data = bytearray([x%256 for x in range(length)])
axi_ram_inst.write_mem(axi_addr & 0xffff80, b'\x55'*(len(test_data)+256)) axi_ram_inst.write_mem(axi_addr & 0xffff80, b'\x55'*(len(test_data)+256))
mem_data[pcie_addr & 0xffff80:(pcie_addr & 0xffff80)+len(test_data)+256] = b'\xaa'*(len(test_data)+256) mem_data[(pcie_addr-1) & 0xffff80:((pcie_addr-1) & 0xffff80)+len(test_data)+256] = b'\xaa'*(len(test_data)+256)
axi_ram_inst.write_mem(axi_addr, test_data) axi_ram_inst.write_mem(axi_addr, test_data)
data = axi_ram_inst.read_mem(axi_addr&0xfffff0, 64) data = axi_ram_inst.read_mem(axi_addr&0xfffff0, 64)

6
tb/test_pcie_us_axi_dma_wr_256.py
View File

@ -393,8 +393,8 @@ def bench():
print("test 3: various writes") print("test 3: various writes")
current_test.next = 3 current_test.next = 3
for length in list(range(1,35))+[1024]: for length in list(range(1,35))+list(range(128-4,128+4))+[1024]:
for pcie_offset in list(range(8,13))+list(range(4096-4,4096)): for pcie_offset in list(range(8,13))+list(range(4096-4,4096+4)):
for axi_offset in list(range(8,41))+list(range(4096-32,4096)): for axi_offset in list(range(8,41))+list(range(4096-32,4096)):
for pause in [False, True]: for pause in [False, True]:
print("length %d, pcie_offset %d, axi_offset %d"% (length, pcie_offset, axi_offset)) print("length %d, pcie_offset %d, axi_offset %d"% (length, pcie_offset, axi_offset))
@ -404,7 +404,7 @@ def bench():
test_data = bytearray([x%256 for x in range(length)]) test_data = bytearray([x%256 for x in range(length)])
axi_ram_inst.write_mem(axi_addr & 0xffff80, b'\x55'*(len(test_data)+256)) axi_ram_inst.write_mem(axi_addr & 0xffff80, b'\x55'*(len(test_data)+256))
mem_data[pcie_addr & 0xffff80:(pcie_addr & 0xffff80)+len(test_data)+256] = b'\xaa'*(len(test_data)+256) mem_data[(pcie_addr-1) & 0xffff80:((pcie_addr-1) & 0xffff80)+len(test_data)+256] = b'\xaa'*(len(test_data)+256)
axi_ram_inst.write_mem(axi_addr, test_data) axi_ram_inst.write_mem(axi_addr, test_data)
data = axi_ram_inst.read_mem(axi_addr&0xfffff0, 64) data = axi_ram_inst.read_mem(axi_addr&0xfffff0, 64)

7
tb/test_pcie_us_axi_dma_wr_64.py
View File

@ -393,8 +393,8 @@ def bench():
print("test 3: various writes") print("test 3: various writes")
current_test.next = 3 current_test.next = 3
for length in list(range(1,11))+[1024]: for length in list(range(1,11))+list(range(128-4,128+4))+[1024]:
for pcie_offset in list(range(8,13))+list(range(4096-4,4096)): for pcie_offset in list(range(8,13))+list(range(4096-4,4096+4)):
for axi_offset in list(range(8,17))+list(range(4096-8,4096)): for axi_offset in list(range(8,17))+list(range(4096-8,4096)):
for pause in [False, True]: for pause in [False, True]:
print("length %d, pcie_offset %d, axi_offset %d"% (length, pcie_offset, axi_offset)) print("length %d, pcie_offset %d, axi_offset %d"% (length, pcie_offset, axi_offset))
@ -404,7 +404,7 @@ def bench():
test_data = bytearray([x%256 for x in range(length)]) test_data = bytearray([x%256 for x in range(length)])
axi_ram_inst.write_mem(axi_addr & 0xffff80, b'\x55'*(len(test_data)+256)) axi_ram_inst.write_mem(axi_addr & 0xffff80, b'\x55'*(len(test_data)+256))
mem_data[pcie_addr & 0xffff80:(pcie_addr & 0xffff80)+len(test_data)+256] = b'\xaa'*(len(test_data)+256) mem_data[(pcie_addr-1) & 0xffff80:((pcie_addr-1) & 0xffff80)+len(test_data)+256] = b'\xaa'*(len(test_data)+256)
axi_ram_inst.write_mem(axi_addr, test_data) axi_ram_inst.write_mem(axi_addr, test_data)
data = axi_ram_inst.read_mem(axi_addr&0xfffff0, 64) data = axi_ram_inst.read_mem(axi_addr&0xfffff0, 64)
@ -430,6 +430,7 @@ def bench():
for i in range(0, len(data), 16): for i in range(0, len(data), 16):
print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16])))) print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
print(mem_data[pcie_addr-1:pcie_addr+len(test_data)+1])
assert mem_data[pcie_addr-1:pcie_addr+len(test_data)+1] == b'\xaa'+test_data+b'\xaa' assert mem_data[pcie_addr-1:pcie_addr+len(test_data)+1] == b'\xaa'+test_data+b'\xaa'
cur_tag = (cur_tag + 1) % 256 cur_tag = (cur_tag + 1) % 256