From bdfeaa84ca3ad287bbe069f5369de91f8a764557 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Sat, 6 Mar 2021 20:06:23 -0800 Subject: [PATCH] Update testbenches --- .../tb/fpga_core/test_fpga_core.py | 13 ++++------ .../fpga_axi/tb/fpga_core/test_fpga_core.py | 13 ++++------ .../fpga_axi/tb/fpga_core/test_fpga_core.py | 13 ++++------ .../fpga_axi/tb/fpga_core/test_fpga_core.py | 13 ++++------ .../fpga_axi/tb/fpga_core/test_fpga_core.py | 13 ++++------ .../fpga_axi/tb/fpga_core/test_fpga_core.py | 25 +++++++------------ .../fpga_axi/tb/fpga_core/test_fpga_core.py | 13 ++++------ .../fpga_axi/tb/fpga_core/test_fpga_core.py | 25 +++++++------------ .../tb/fpga_core/test_fpga_core.py | 13 ++++------ .../fpga_axi/tb/fpga_core/test_fpga_core.py | 13 ++++------ .../fpga_axi/tb/fpga_core/test_fpga_core.py | 13 ++++------ .../fpga_axi/tb/fpga_core/test_fpga_core.py | 13 ++++------ .../test_dma_client_axis_sink.py | 12 ++++----- .../test_dma_client_axis_source.py | 12 ++++----- tb/dma_if_pcie_us/test_dma_if_pcie_us.py | 19 +++++++------- .../test_dma_if_pcie_us_rd.py | 15 ++++++----- .../test_dma_if_pcie_us_wr.py | 12 ++++----- tb/pcie_us_axi_dma/test_pcie_us_axi_dma.py | 23 ++++++++--------- .../test_pcie_us_axi_dma_rd.py | 19 +++++++------- .../test_pcie_us_axi_dma_wr.py | 16 ++++++------ .../test_pcie_us_axi_master.py | 11 ++++---- .../test_pcie_us_axi_master_rd.py | 11 ++++---- .../test_pcie_us_axi_master_wr.py | 8 +++--- .../test_pcie_us_axil_master.py | 11 ++++---- 24 files changed, 149 insertions(+), 200 deletions(-) diff --git a/example/ADM_PCIE_9V3/fpga_axi_x8/tb/fpga_core/test_fpga_core.py b/example/ADM_PCIE_9V3/fpga_axi_x8/tb/fpga_core/test_fpga_core.py index 34d119c..e93dfd3 100644 --- a/example/ADM_PCIE_9V3/fpga_axi_x8/tb/fpga_core/test_fpga_core.py +++ b/example/ADM_PCIE_9V3/fpga_axi_x8/tb/fpga_core/test_fpga_core.py @@ -31,6 +31,7 @@ import cocotb from cocotb.log import SimLog from cocotb.triggers import RisingEdge, FallingEdge, Timer +from cocotbext.axi import AxiStreamBus from cocotbext.pcie.core import RootComplex from cocotbext.pcie.xilinx.us import UltraScalePlusPcieDevice from cocotbext.axi.utils import hexdump_str @@ -77,8 +78,7 @@ class TB(object): # phy_rdy_out # Requester reQuest Interface - rq_entity=dut, - rq_name="m_axis_rq", + rq_bus=AxiStreamBus.from_prefix(dut, "m_axis_rq"), # pcie_rq_seq_num0=dut.s_axis_rq_seq_num_0, # pcie_rq_seq_num_vld0=dut.s_axis_rq_seq_num_valid_0, # pcie_rq_seq_num1=dut.s_axis_rq_seq_num_1, @@ -90,18 +90,15 @@ class TB(object): # pcie_rq_tag_vld1 # Requester Completion Interface - rc_entity=dut, - rc_name="s_axis_rc", + rc_bus=AxiStreamBus.from_prefix(dut, "s_axis_rc"), # Completer reQuest Interface - cq_entity=dut, - cq_name="s_axis_cq", + cq_bus=AxiStreamBus.from_prefix(dut, "s_axis_cq"), # pcie_cq_np_req # pcie_cq_np_req_count # Completer Completion Interface - cc_entity=dut, - cc_name="m_axis_cc", + cc_bus=AxiStreamBus.from_prefix(dut, "m_axis_cc"), # Transmit Flow Control Interface # pcie_tfc_nph_av=dut.pcie_tfc_nph_av, diff --git a/example/AU200/fpga_axi/tb/fpga_core/test_fpga_core.py b/example/AU200/fpga_axi/tb/fpga_core/test_fpga_core.py index c904964..f45ed9c 100644 --- a/example/AU200/fpga_axi/tb/fpga_core/test_fpga_core.py +++ b/example/AU200/fpga_axi/tb/fpga_core/test_fpga_core.py @@ -31,6 +31,7 @@ import cocotb from cocotb.log import SimLog from cocotb.triggers import RisingEdge, FallingEdge, Timer +from cocotbext.axi import AxiStreamBus from cocotbext.pcie.core import RootComplex from cocotbext.pcie.xilinx.us import UltraScalePlusPcieDevice from cocotbext.axi.utils import hexdump_str @@ -77,8 +78,7 @@ class TB(object): # phy_rdy_out # Requester reQuest Interface - rq_entity=dut, - rq_name="m_axis_rq", + rq_bus=AxiStreamBus.from_prefix(dut, "m_axis_rq"), # pcie_rq_seq_num0=dut.s_axis_rq_seq_num_0, # pcie_rq_seq_num_vld0=dut.s_axis_rq_seq_num_valid_0, # pcie_rq_seq_num1=dut.s_axis_rq_seq_num_1, @@ -90,18 +90,15 @@ class TB(object): # pcie_rq_tag_vld1 # Requester Completion Interface - rc_entity=dut, - rc_name="s_axis_rc", + rc_bus=AxiStreamBus.from_prefix(dut, "s_axis_rc"), # Completer reQuest Interface - cq_entity=dut, - cq_name="s_axis_cq", + cq_bus=AxiStreamBus.from_prefix(dut, "s_axis_cq"), # pcie_cq_np_req # pcie_cq_np_req_count # Completer Completion Interface - cc_entity=dut, - cc_name="m_axis_cc", + cc_bus=AxiStreamBus.from_prefix(dut, "m_axis_cc"), # Transmit Flow Control Interface # pcie_tfc_nph_av=dut.pcie_tfc_nph_av, diff --git a/example/AU250/fpga_axi/tb/fpga_core/test_fpga_core.py b/example/AU250/fpga_axi/tb/fpga_core/test_fpga_core.py index c904964..f45ed9c 100644 --- a/example/AU250/fpga_axi/tb/fpga_core/test_fpga_core.py +++ b/example/AU250/fpga_axi/tb/fpga_core/test_fpga_core.py @@ -31,6 +31,7 @@ import cocotb from cocotb.log import SimLog from cocotb.triggers import RisingEdge, FallingEdge, Timer +from cocotbext.axi import AxiStreamBus from cocotbext.pcie.core import RootComplex from cocotbext.pcie.xilinx.us import UltraScalePlusPcieDevice from cocotbext.axi.utils import hexdump_str @@ -77,8 +78,7 @@ class TB(object): # phy_rdy_out # Requester reQuest Interface - rq_entity=dut, - rq_name="m_axis_rq", + rq_bus=AxiStreamBus.from_prefix(dut, "m_axis_rq"), # pcie_rq_seq_num0=dut.s_axis_rq_seq_num_0, # pcie_rq_seq_num_vld0=dut.s_axis_rq_seq_num_valid_0, # pcie_rq_seq_num1=dut.s_axis_rq_seq_num_1, @@ -90,18 +90,15 @@ class TB(object): # pcie_rq_tag_vld1 # Requester Completion Interface - rc_entity=dut, - rc_name="s_axis_rc", + rc_bus=AxiStreamBus.from_prefix(dut, "s_axis_rc"), # Completer reQuest Interface - cq_entity=dut, - cq_name="s_axis_cq", + cq_bus=AxiStreamBus.from_prefix(dut, "s_axis_cq"), # pcie_cq_np_req # pcie_cq_np_req_count # Completer Completion Interface - cc_entity=dut, - cc_name="m_axis_cc", + cc_bus=AxiStreamBus.from_prefix(dut, "m_axis_cc"), # Transmit Flow Control Interface # pcie_tfc_nph_av=dut.pcie_tfc_nph_av, diff --git a/example/AU280/fpga_axi/tb/fpga_core/test_fpga_core.py b/example/AU280/fpga_axi/tb/fpga_core/test_fpga_core.py index 5bb0a99..fba7162 100644 --- a/example/AU280/fpga_axi/tb/fpga_core/test_fpga_core.py +++ b/example/AU280/fpga_axi/tb/fpga_core/test_fpga_core.py @@ -31,6 +31,7 @@ import cocotb from cocotb.log import SimLog from cocotb.triggers import RisingEdge, FallingEdge, Timer +from cocotbext.axi import AxiStreamBus from cocotbext.pcie.core import RootComplex from cocotbext.pcie.xilinx.us import UltraScalePlusPcieDevice from cocotbext.axi.utils import hexdump_str @@ -77,8 +78,7 @@ class TB(object): # phy_rdy_out # Requester reQuest Interface - rq_entity=dut, - rq_name="m_axis_rq", + rq_bus=AxiStreamBus.from_prefix(dut, "m_axis_rq"), # pcie_rq_seq_num0=dut.s_axis_rq_seq_num_0, # pcie_rq_seq_num_vld0=dut.s_axis_rq_seq_num_valid_0, # pcie_rq_seq_num1=dut.s_axis_rq_seq_num_1, @@ -90,18 +90,15 @@ class TB(object): # pcie_rq_tag_vld1 # Requester Completion Interface - rc_entity=dut, - rc_name="s_axis_rc", + rc_bus=AxiStreamBus.from_prefix(dut, "s_axis_rc"), # Completer reQuest Interface - cq_entity=dut, - cq_name="s_axis_cq", + cq_bus=AxiStreamBus.from_prefix(dut, "s_axis_cq"), # pcie_cq_np_req # pcie_cq_np_req_count # Completer Completion Interface - cc_entity=dut, - cc_name="m_axis_cc", + cc_bus=AxiStreamBus.from_prefix(dut, "m_axis_cc"), # Transmit Flow Control Interface # pcie_tfc_nph_av=dut.pcie_tfc_nph_av, diff --git a/example/AU50/fpga_axi/tb/fpga_core/test_fpga_core.py b/example/AU50/fpga_axi/tb/fpga_core/test_fpga_core.py index 5bb0a99..fba7162 100644 --- a/example/AU50/fpga_axi/tb/fpga_core/test_fpga_core.py +++ b/example/AU50/fpga_axi/tb/fpga_core/test_fpga_core.py @@ -31,6 +31,7 @@ import cocotb from cocotb.log import SimLog from cocotb.triggers import RisingEdge, FallingEdge, Timer +from cocotbext.axi import AxiStreamBus from cocotbext.pcie.core import RootComplex from cocotbext.pcie.xilinx.us import UltraScalePlusPcieDevice from cocotbext.axi.utils import hexdump_str @@ -77,8 +78,7 @@ class TB(object): # phy_rdy_out # Requester reQuest Interface - rq_entity=dut, - rq_name="m_axis_rq", + rq_bus=AxiStreamBus.from_prefix(dut, "m_axis_rq"), # pcie_rq_seq_num0=dut.s_axis_rq_seq_num_0, # pcie_rq_seq_num_vld0=dut.s_axis_rq_seq_num_valid_0, # pcie_rq_seq_num1=dut.s_axis_rq_seq_num_1, @@ -90,18 +90,15 @@ class TB(object): # pcie_rq_tag_vld1 # Requester Completion Interface - rc_entity=dut, - rc_name="s_axis_rc", + rc_bus=AxiStreamBus.from_prefix(dut, "s_axis_rc"), # Completer reQuest Interface - cq_entity=dut, - cq_name="s_axis_cq", + cq_bus=AxiStreamBus.from_prefix(dut, "s_axis_cq"), # pcie_cq_np_req # pcie_cq_np_req_count # Completer Completion Interface - cc_entity=dut, - cc_name="m_axis_cc", + cc_bus=AxiStreamBus.from_prefix(dut, "m_axis_cc"), # Transmit Flow Control Interface # pcie_tfc_nph_av=dut.pcie_tfc_nph_av, diff --git a/example/ExaNIC_X10/fpga_axi/tb/fpga_core/test_fpga_core.py b/example/ExaNIC_X10/fpga_axi/tb/fpga_core/test_fpga_core.py index 9983823..70c089c 100644 --- a/example/ExaNIC_X10/fpga_axi/tb/fpga_core/test_fpga_core.py +++ b/example/ExaNIC_X10/fpga_axi/tb/fpga_core/test_fpga_core.py @@ -31,6 +31,7 @@ import cocotb from cocotb.log import SimLog from cocotb.triggers import RisingEdge, FallingEdge, Timer +from cocotbext.axi import AxiStreamBus from cocotbext.pcie.core import RootComplex from cocotbext.pcie.xilinx.us import UltraScalePcieDevice from cocotbext.axi.utils import hexdump_str @@ -75,31 +76,23 @@ class TB(object): # phy_rdy_out # Requester reQuest Interface - rq_entity=dut, - rq_name="m_axis_rq", - # pcie_rq_seq_num0=dut.s_axis_rq_seq_num_0, - # pcie_rq_seq_num_vld0=dut.s_axis_rq_seq_num_valid_0, - # pcie_rq_seq_num1=dut.s_axis_rq_seq_num_1, - # pcie_rq_seq_num_vld1=dut.s_axis_rq_seq_num_valid_1, - # pcie_rq_tag0 - # pcie_rq_tag1 + rq_bus=AxiStreamBus.from_prefix(dut, "m_axis_rq"), + # pcie_rq_seq_num=dut.s_axis_rq_seq_num, + # pcie_rq_seq_num_vld=dut.s_axis_rq_seq_num_valid, + # pcie_rq_tag # pcie_rq_tag_av - # pcie_rq_tag_vld0 - # pcie_rq_tag_vld1 + # pcie_rq_tag_vld # Requester Completion Interface - rc_entity=dut, - rc_name="s_axis_rc", + rc_bus=AxiStreamBus.from_prefix(dut, "s_axis_rc"), # Completer reQuest Interface - cq_entity=dut, - cq_name="s_axis_cq", + cq_bus=AxiStreamBus.from_prefix(dut, "s_axis_cq"), # pcie_cq_np_req # pcie_cq_np_req_count # Completer Completion Interface - cc_entity=dut, - cc_name="m_axis_cc", + cc_bus=AxiStreamBus.from_prefix(dut, "m_axis_cc"), # Transmit Flow Control Interface # pcie_tfc_nph_av=dut.pcie_tfc_nph_av, diff --git a/example/ExaNIC_X25/fpga_axi/tb/fpga_core/test_fpga_core.py b/example/ExaNIC_X25/fpga_axi/tb/fpga_core/test_fpga_core.py index 34d119c..e93dfd3 100644 --- a/example/ExaNIC_X25/fpga_axi/tb/fpga_core/test_fpga_core.py +++ b/example/ExaNIC_X25/fpga_axi/tb/fpga_core/test_fpga_core.py @@ -31,6 +31,7 @@ import cocotb from cocotb.log import SimLog from cocotb.triggers import RisingEdge, FallingEdge, Timer +from cocotbext.axi import AxiStreamBus from cocotbext.pcie.core import RootComplex from cocotbext.pcie.xilinx.us import UltraScalePlusPcieDevice from cocotbext.axi.utils import hexdump_str @@ -77,8 +78,7 @@ class TB(object): # phy_rdy_out # Requester reQuest Interface - rq_entity=dut, - rq_name="m_axis_rq", + rq_bus=AxiStreamBus.from_prefix(dut, "m_axis_rq"), # pcie_rq_seq_num0=dut.s_axis_rq_seq_num_0, # pcie_rq_seq_num_vld0=dut.s_axis_rq_seq_num_valid_0, # pcie_rq_seq_num1=dut.s_axis_rq_seq_num_1, @@ -90,18 +90,15 @@ class TB(object): # pcie_rq_tag_vld1 # Requester Completion Interface - rc_entity=dut, - rc_name="s_axis_rc", + rc_bus=AxiStreamBus.from_prefix(dut, "s_axis_rc"), # Completer reQuest Interface - cq_entity=dut, - cq_name="s_axis_cq", + cq_bus=AxiStreamBus.from_prefix(dut, "s_axis_cq"), # pcie_cq_np_req # pcie_cq_np_req_count # Completer Completion Interface - cc_entity=dut, - cc_name="m_axis_cc", + cc_bus=AxiStreamBus.from_prefix(dut, "m_axis_cc"), # Transmit Flow Control Interface # pcie_tfc_nph_av=dut.pcie_tfc_nph_av, diff --git a/example/VCU108/fpga_axi/tb/fpga_core/test_fpga_core.py b/example/VCU108/fpga_axi/tb/fpga_core/test_fpga_core.py index d06c414..5d59c7a 100644 --- a/example/VCU108/fpga_axi/tb/fpga_core/test_fpga_core.py +++ b/example/VCU108/fpga_axi/tb/fpga_core/test_fpga_core.py @@ -31,6 +31,7 @@ import cocotb from cocotb.log import SimLog from cocotb.triggers import RisingEdge, FallingEdge, Timer +from cocotbext.axi import AxiStreamBus from cocotbext.pcie.core import RootComplex from cocotbext.pcie.xilinx.us import UltraScalePcieDevice from cocotbext.axi.utils import hexdump_str @@ -75,31 +76,23 @@ class TB(object): # phy_rdy_out # Requester reQuest Interface - rq_entity=dut, - rq_name="m_axis_rq", - # pcie_rq_seq_num0=dut.s_axis_rq_seq_num_0, - # pcie_rq_seq_num_vld0=dut.s_axis_rq_seq_num_valid_0, - # pcie_rq_seq_num1=dut.s_axis_rq_seq_num_1, - # pcie_rq_seq_num_vld1=dut.s_axis_rq_seq_num_valid_1, - # pcie_rq_tag0 - # pcie_rq_tag1 + rq_bus=AxiStreamBus.from_prefix(dut, "m_axis_rq"), + # pcie_rq_seq_num=dut.s_axis_rq_seq_num, + # pcie_rq_seq_num_vld=dut.s_axis_rq_seq_num_valid, + # pcie_rq_tag # pcie_rq_tag_av - # pcie_rq_tag_vld0 - # pcie_rq_tag_vld1 + # pcie_rq_tag_vld # Requester Completion Interface - rc_entity=dut, - rc_name="s_axis_rc", + rc_bus=AxiStreamBus.from_prefix(dut, "s_axis_rc"), # Completer reQuest Interface - cq_entity=dut, - cq_name="s_axis_cq", + cq_bus=AxiStreamBus.from_prefix(dut, "s_axis_cq"), # pcie_cq_np_req # pcie_cq_np_req_count # Completer Completion Interface - cc_entity=dut, - cc_name="m_axis_cc", + cc_bus=AxiStreamBus.from_prefix(dut, "m_axis_cc"), # Transmit Flow Control Interface # pcie_tfc_nph_av=dut.pcie_tfc_nph_av, diff --git a/example/VCU118/fpga_axi_x8/tb/fpga_core/test_fpga_core.py b/example/VCU118/fpga_axi_x8/tb/fpga_core/test_fpga_core.py index 6b5556b..b42a57e 100644 --- a/example/VCU118/fpga_axi_x8/tb/fpga_core/test_fpga_core.py +++ b/example/VCU118/fpga_axi_x8/tb/fpga_core/test_fpga_core.py @@ -31,6 +31,7 @@ import cocotb from cocotb.log import SimLog from cocotb.triggers import RisingEdge, FallingEdge, Timer +from cocotbext.axi import AxiStreamBus from cocotbext.pcie.core import RootComplex from cocotbext.pcie.xilinx.us import UltraScalePlusPcieDevice from cocotbext.axi.utils import hexdump_str @@ -77,8 +78,7 @@ class TB(object): # phy_rdy_out # Requester reQuest Interface - rq_entity=dut, - rq_name="m_axis_rq", + rq_bus=AxiStreamBus.from_prefix(dut, "m_axis_rq"), # pcie_rq_seq_num0=dut.s_axis_rq_seq_num_0, # pcie_rq_seq_num_vld0=dut.s_axis_rq_seq_num_valid_0, # pcie_rq_seq_num1=dut.s_axis_rq_seq_num_1, @@ -90,18 +90,15 @@ class TB(object): # pcie_rq_tag_vld1 # Requester Completion Interface - rc_entity=dut, - rc_name="s_axis_rc", + rc_bus=AxiStreamBus.from_prefix(dut, "s_axis_rc"), # Completer reQuest Interface - cq_entity=dut, - cq_name="s_axis_cq", + cq_bus=AxiStreamBus.from_prefix(dut, "s_axis_cq"), # pcie_cq_np_req # pcie_cq_np_req_count # Completer Completion Interface - cc_entity=dut, - cc_name="m_axis_cc", + cc_bus=AxiStreamBus.from_prefix(dut, "m_axis_cc"), # Transmit Flow Control Interface # pcie_tfc_nph_av=dut.pcie_tfc_nph_av, diff --git a/example/VCU1525/fpga_axi/tb/fpga_core/test_fpga_core.py b/example/VCU1525/fpga_axi/tb/fpga_core/test_fpga_core.py index c904964..f45ed9c 100644 --- a/example/VCU1525/fpga_axi/tb/fpga_core/test_fpga_core.py +++ b/example/VCU1525/fpga_axi/tb/fpga_core/test_fpga_core.py @@ -31,6 +31,7 @@ import cocotb from cocotb.log import SimLog from cocotb.triggers import RisingEdge, FallingEdge, Timer +from cocotbext.axi import AxiStreamBus from cocotbext.pcie.core import RootComplex from cocotbext.pcie.xilinx.us import UltraScalePlusPcieDevice from cocotbext.axi.utils import hexdump_str @@ -77,8 +78,7 @@ class TB(object): # phy_rdy_out # Requester reQuest Interface - rq_entity=dut, - rq_name="m_axis_rq", + rq_bus=AxiStreamBus.from_prefix(dut, "m_axis_rq"), # pcie_rq_seq_num0=dut.s_axis_rq_seq_num_0, # pcie_rq_seq_num_vld0=dut.s_axis_rq_seq_num_valid_0, # pcie_rq_seq_num1=dut.s_axis_rq_seq_num_1, @@ -90,18 +90,15 @@ class TB(object): # pcie_rq_tag_vld1 # Requester Completion Interface - rc_entity=dut, - rc_name="s_axis_rc", + rc_bus=AxiStreamBus.from_prefix(dut, "s_axis_rc"), # Completer reQuest Interface - cq_entity=dut, - cq_name="s_axis_cq", + cq_bus=AxiStreamBus.from_prefix(dut, "s_axis_cq"), # pcie_cq_np_req # pcie_cq_np_req_count # Completer Completion Interface - cc_entity=dut, - cc_name="m_axis_cc", + cc_bus=AxiStreamBus.from_prefix(dut, "m_axis_cc"), # Transmit Flow Control Interface # pcie_tfc_nph_av=dut.pcie_tfc_nph_av, diff --git a/example/ZCU106/fpga_axi/tb/fpga_core/test_fpga_core.py b/example/ZCU106/fpga_axi/tb/fpga_core/test_fpga_core.py index d07550c..89c00a0 100644 --- a/example/ZCU106/fpga_axi/tb/fpga_core/test_fpga_core.py +++ b/example/ZCU106/fpga_axi/tb/fpga_core/test_fpga_core.py @@ -31,6 +31,7 @@ import cocotb from cocotb.log import SimLog from cocotb.triggers import RisingEdge, FallingEdge, Timer +from cocotbext.axi import AxiStreamBus from cocotbext.pcie.core import RootComplex from cocotbext.pcie.xilinx.us import UltraScalePlusPcieDevice from cocotbext.axi.utils import hexdump_str @@ -77,8 +78,7 @@ class TB(object): # phy_rdy_out # Requester reQuest Interface - rq_entity=dut, - rq_name="m_axis_rq", + rq_bus=AxiStreamBus.from_prefix(dut, "m_axis_rq"), # pcie_rq_seq_num0=dut.s_axis_rq_seq_num_0, # pcie_rq_seq_num_vld0=dut.s_axis_rq_seq_num_valid_0, # pcie_rq_seq_num1=dut.s_axis_rq_seq_num_1, @@ -90,18 +90,15 @@ class TB(object): # pcie_rq_tag_vld1 # Requester Completion Interface - rc_entity=dut, - rc_name="s_axis_rc", + rc_bus=AxiStreamBus.from_prefix(dut, "s_axis_rc"), # Completer reQuest Interface - cq_entity=dut, - cq_name="s_axis_cq", + cq_bus=AxiStreamBus.from_prefix(dut, "s_axis_cq"), # pcie_cq_np_req # pcie_cq_np_req_count # Completer Completion Interface - cc_entity=dut, - cc_name="m_axis_cc", + cc_bus=AxiStreamBus.from_prefix(dut, "m_axis_cc"), # Transmit Flow Control Interface # pcie_tfc_nph_av=dut.pcie_tfc_nph_av, diff --git a/example/fb2CG/fpga_axi/tb/fpga_core/test_fpga_core.py b/example/fb2CG/fpga_axi/tb/fpga_core/test_fpga_core.py index 5bb0a99..fba7162 100644 --- a/example/fb2CG/fpga_axi/tb/fpga_core/test_fpga_core.py +++ b/example/fb2CG/fpga_axi/tb/fpga_core/test_fpga_core.py @@ -31,6 +31,7 @@ import cocotb from cocotb.log import SimLog from cocotb.triggers import RisingEdge, FallingEdge, Timer +from cocotbext.axi import AxiStreamBus from cocotbext.pcie.core import RootComplex from cocotbext.pcie.xilinx.us import UltraScalePlusPcieDevice from cocotbext.axi.utils import hexdump_str @@ -77,8 +78,7 @@ class TB(object): # phy_rdy_out # Requester reQuest Interface - rq_entity=dut, - rq_name="m_axis_rq", + rq_bus=AxiStreamBus.from_prefix(dut, "m_axis_rq"), # pcie_rq_seq_num0=dut.s_axis_rq_seq_num_0, # pcie_rq_seq_num_vld0=dut.s_axis_rq_seq_num_valid_0, # pcie_rq_seq_num1=dut.s_axis_rq_seq_num_1, @@ -90,18 +90,15 @@ class TB(object): # pcie_rq_tag_vld1 # Requester Completion Interface - rc_entity=dut, - rc_name="s_axis_rc", + rc_bus=AxiStreamBus.from_prefix(dut, "s_axis_rc"), # Completer reQuest Interface - cq_entity=dut, - cq_name="s_axis_cq", + cq_bus=AxiStreamBus.from_prefix(dut, "s_axis_cq"), # pcie_cq_np_req # pcie_cq_np_req_count # Completer Completion Interface - cc_entity=dut, - cc_name="m_axis_cc", + cc_bus=AxiStreamBus.from_prefix(dut, "m_axis_cc"), # Transmit Flow Control Interface # pcie_tfc_nph_av=dut.pcie_tfc_nph_av, diff --git a/tb/dma_client_axis_sink/test_dma_client_axis_sink.py b/tb/dma_client_axis_sink/test_dma_client_axis_sink.py index b8eb720..25eb114 100644 --- a/tb/dma_client_axis_sink/test_dma_client_axis_sink.py +++ b/tb/dma_client_axis_sink/test_dma_client_axis_sink.py @@ -35,7 +35,7 @@ from cocotb.clock import Clock from cocotb.triggers import RisingEdge from cocotb.regression import TestFactory -from cocotbext.axi import AxiStreamFrame, AxiStreamSource +from cocotbext.axi import AxiStreamBus, AxiStreamFrame, AxiStreamSource from cocotbext.axi.stream import define_stream try: @@ -48,12 +48,12 @@ except ImportError: finally: del sys.path[0] -DescTransaction, DescSource, DescSink, DescMonitor = define_stream("Desc", +DescBus, DescTransaction, DescSource, DescSink, DescMonitor = define_stream("Desc", signals=["ram_addr", "len", "tag", "valid", "ready"], optional_signals=["id", "dest", "user"] ) -DescStatusTransaction, DescStatusSource, DescStatusSink, DescStatusMonitor = define_stream("DescStatus", +DescStatusBus, DescStatusTransaction, DescStatusSource, DescStatusSink, DescStatusMonitor = define_stream("DescStatus", signals=["tag", "valid"], optional_signals=["len", "id", "dest", "user"] ) @@ -69,9 +69,9 @@ class TB(object): cocotb.fork(Clock(dut.clk, 4, units="ns").start()) # write interface - self.write_desc_source = DescSource(dut, "s_axis_write_desc", dut.clk, dut.rst) - self.write_desc_status_sink = DescStatusSink(dut, "m_axis_write_desc_status", dut.clk, dut.rst) - self.write_data_source = AxiStreamSource(dut, "s_axis_write_data", dut.clk, dut.rst) + self.write_desc_source = DescSource(DescBus.from_prefix(dut, "s_axis_write_desc"), dut.clk, dut.rst) + self.write_desc_status_sink = DescStatusSink(DescStatusBus.from_prefix(dut, "m_axis_write_desc_status"), dut.clk, dut.rst) + self.write_data_source = AxiStreamSource(AxiStreamBus.from_prefix(dut, "s_axis_write_data"), dut.clk, dut.rst) # DMA RAM self.dma_ram = PsdpRamWrite(dut, "ram", dut.clk, dut.rst, size=2**16) diff --git a/tb/dma_client_axis_source/test_dma_client_axis_source.py b/tb/dma_client_axis_source/test_dma_client_axis_source.py index 2d091c6..5dbcfe4 100644 --- a/tb/dma_client_axis_source/test_dma_client_axis_source.py +++ b/tb/dma_client_axis_source/test_dma_client_axis_source.py @@ -35,7 +35,7 @@ from cocotb.clock import Clock from cocotb.triggers import RisingEdge from cocotb.regression import TestFactory -from cocotbext.axi import AxiStreamSink +from cocotbext.axi import AxiStreamBus, AxiStreamSink from cocotbext.axi.stream import define_stream try: @@ -48,12 +48,12 @@ except ImportError: finally: del sys.path[0] -DescTransaction, DescSource, DescSink, DescMonitor = define_stream("Desc", +DescBus, DescTransaction, DescSource, DescSink, DescMonitor = define_stream("Desc", signals=["ram_addr", "len", "tag", "valid", "ready"], optional_signals=["id", "dest", "user"] ) -DescStatusTransaction, DescStatusSource, DescStatusSink, DescStatusMonitor = define_stream("DescStatus", +DescStatusBus, DescStatusTransaction, DescStatusSource, DescStatusSink, DescStatusMonitor = define_stream("DescStatus", signals=["tag", "valid"], optional_signals=["len", "id", "dest", "user"] ) @@ -69,9 +69,9 @@ class TB(object): cocotb.fork(Clock(dut.clk, 4, units="ns").start()) # read interface - self.read_desc_source = DescSource(dut, "s_axis_read_desc", dut.clk, dut.rst) - self.read_desc_status_sink = DescStatusSink(dut, "m_axis_read_desc_status", dut.clk, dut.rst) - self.read_data_sink = AxiStreamSink(dut, "m_axis_read_data", dut.clk, dut.rst) + self.read_desc_source = DescSource(DescBus.from_prefix(dut, "s_axis_read_desc"), dut.clk, dut.rst) + self.read_desc_status_sink = DescStatusSink(DescStatusBus.from_prefix(dut, "m_axis_read_desc_status"), dut.clk, dut.rst) + self.read_data_sink = AxiStreamSink(AxiStreamBus.from_prefix(dut, "m_axis_read_data"), dut.clk, dut.rst) # DMA RAM self.dma_ram = PsdpRamRead(dut, "ram", dut.clk, dut.rst, size=2**16) diff --git a/tb/dma_if_pcie_us/test_dma_if_pcie_us.py b/tb/dma_if_pcie_us/test_dma_if_pcie_us.py index 0087a5f..3695190 100644 --- a/tb/dma_if_pcie_us/test_dma_if_pcie_us.py +++ b/tb/dma_if_pcie_us/test_dma_if_pcie_us.py @@ -35,6 +35,7 @@ import cocotb from cocotb.triggers import RisingEdge, FallingEdge, Timer from cocotb.regression import TestFactory +from cocotbext.axi import AxiStreamBus from cocotbext.pcie.core import RootComplex from cocotbext.pcie.xilinx.us import UltraScalePlusPcieDevice from cocotbext.axi.stream import define_stream @@ -51,11 +52,11 @@ except ImportError: del sys.path[0] -DescTransaction, DescSource, DescSink, DescMonitor = define_stream("Desc", +DescBus, DescTransaction, DescSource, DescSink, DescMonitor = define_stream("Desc", signals=["pcie_addr", "ram_addr", "ram_sel", "len", "tag", "valid", "ready"] ) -DescStatusTransaction, DescStatusSource, DescStatusSink, DescStatusMonitor = define_stream("DescStatus", +DescStatusBus, DescStatusTransaction, DescStatusSource, DescStatusSink, DescStatusMonitor = define_stream("DescStatus", signals=["tag", "valid"] ) @@ -94,15 +95,13 @@ class TB(object): user_clk=dut.clk, user_reset=dut.rst, - rq_entity=dut, - rq_name="m_axis_rq", + rq_bus=AxiStreamBus.from_prefix(dut, "m_axis_rq"), pcie_rq_seq_num0=dut.s_axis_rq_seq_num_0, pcie_rq_seq_num_vld0=dut.s_axis_rq_seq_num_valid_0, pcie_rq_seq_num1=dut.s_axis_rq_seq_num_1, pcie_rq_seq_num_vld1=dut.s_axis_rq_seq_num_valid_1, - rc_entity=dut, - rc_name="s_axis_rc", + rc_bus=AxiStreamBus.from_prefix(dut, "s_axis_rc"), cfg_max_payload=dut.max_payload_size, cfg_max_read_req=dut.max_read_request_size, @@ -121,11 +120,11 @@ class TB(object): self.dma_ram = PsdpRam(dut, "ram", dut.clk, dut.rst, size=2**16) # Control - self.read_desc_source = DescSource(dut, "s_axis_read_desc", dut.clk, dut.rst) - self.read_desc_status_sink = DescStatusSink(dut, "m_axis_read_desc_status", dut.clk, dut.rst) + self.read_desc_source = DescSource(DescBus.from_prefix(dut, "s_axis_read_desc"), dut.clk, dut.rst) + self.read_desc_status_sink = DescStatusSink(DescStatusBus.from_prefix(dut, "m_axis_read_desc_status"), dut.clk, dut.rst) - self.write_desc_source = DescSource(dut, "s_axis_write_desc", dut.clk, dut.rst) - self.write_desc_status_sink = DescStatusSink(dut, "m_axis_write_desc_status", dut.clk, dut.rst) + self.write_desc_source = DescSource(DescBus.from_prefix(dut, "s_axis_write_desc"), dut.clk, dut.rst) + self.write_desc_status_sink = DescStatusSink(DescStatusBus.from_prefix(dut, "m_axis_write_desc_status"), dut.clk, dut.rst) dut.requester_id.setimmediatevalue(0) dut.requester_id_enable.setimmediatevalue(0) diff --git a/tb/dma_if_pcie_us_rd/test_dma_if_pcie_us_rd.py b/tb/dma_if_pcie_us_rd/test_dma_if_pcie_us_rd.py index a1da590..67c013e 100644 --- a/tb/dma_if_pcie_us_rd/test_dma_if_pcie_us_rd.py +++ b/tb/dma_if_pcie_us_rd/test_dma_if_pcie_us_rd.py @@ -35,6 +35,7 @@ import cocotb from cocotb.triggers import RisingEdge, FallingEdge, Timer from cocotb.regression import TestFactory +from cocotbext.axi import AxiStreamBus from cocotbext.pcie.core import RootComplex from cocotbext.pcie.xilinx.us import UltraScalePlusPcieDevice from cocotbext.axi.stream import define_stream @@ -50,11 +51,11 @@ except ImportError: finally: del sys.path[0] -DescTransaction, DescSource, DescSink, DescMonitor = define_stream("Desc", +DescBus, DescTransaction, DescSource, DescSink, DescMonitor = define_stream("Desc", signals=["pcie_addr", "ram_addr", "ram_sel", "len", "tag", "valid", "ready"] ) -DescStatusTransaction, DescStatusSource, DescStatusSink, DescStatusMonitor = define_stream("DescStatus", +DescStatusBus, DescStatusTransaction, DescStatusSource, DescStatusSink, DescStatusMonitor = define_stream("DescStatus", signals=["tag", "valid"] ) @@ -93,15 +94,13 @@ class TB(object): user_clk=dut.clk, user_reset=dut.rst, - rq_entity=dut, - rq_name="m_axis_rq", + rq_bus=AxiStreamBus.from_prefix(dut, "m_axis_rq"), pcie_rq_seq_num0=dut.s_axis_rq_seq_num_0, pcie_rq_seq_num_vld0=dut.s_axis_rq_seq_num_valid_0, pcie_rq_seq_num1=dut.s_axis_rq_seq_num_1, pcie_rq_seq_num_vld1=dut.s_axis_rq_seq_num_valid_1, - rc_entity=dut, - rc_name="s_axis_rc", + rc_bus=AxiStreamBus.from_prefix(dut, "s_axis_rc"), cfg_max_read_req=dut.max_read_request_size, @@ -117,8 +116,8 @@ class TB(object): self.dma_ram = PsdpRamWrite(dut, "ram", dut.clk, dut.rst, size=2**16) # Control - self.read_desc_source = DescSource(dut, "s_axis_read_desc", dut.clk, dut.rst) - self.read_desc_status_sink = DescStatusSink(dut, "m_axis_read_desc_status", dut.clk, dut.rst) + self.read_desc_source = DescSource(DescBus.from_prefix(dut, "s_axis_read_desc"), dut.clk, dut.rst) + self.read_desc_status_sink = DescStatusSink(DescStatusBus.from_prefix(dut, "m_axis_read_desc_status"), dut.clk, dut.rst) dut.requester_id.setimmediatevalue(0) dut.requester_id_enable.setimmediatevalue(0) diff --git a/tb/dma_if_pcie_us_wr/test_dma_if_pcie_us_wr.py b/tb/dma_if_pcie_us_wr/test_dma_if_pcie_us_wr.py index c90448f..9015847 100644 --- a/tb/dma_if_pcie_us_wr/test_dma_if_pcie_us_wr.py +++ b/tb/dma_if_pcie_us_wr/test_dma_if_pcie_us_wr.py @@ -35,6 +35,7 @@ import cocotb from cocotb.triggers import RisingEdge, FallingEdge, Timer from cocotb.regression import TestFactory +from cocotbext.axi import AxiStreamBus from cocotbext.pcie.core import RootComplex from cocotbext.pcie.xilinx.us import UltraScalePlusPcieDevice from cocotbext.axi.stream import define_stream @@ -50,11 +51,11 @@ except ImportError: finally: del sys.path[0] -DescTransaction, DescSource, DescSink, DescMonitor = define_stream("Desc", +DescBus, DescTransaction, DescSource, DescSink, DescMonitor = define_stream("Desc", signals=["pcie_addr", "ram_addr", "ram_sel", "len", "tag", "valid", "ready"] ) -DescStatusTransaction, DescStatusSource, DescStatusSink, DescStatusMonitor = define_stream("DescStatus", +DescStatusBus, DescStatusTransaction, DescStatusSource, DescStatusSink, DescStatusMonitor = define_stream("DescStatus", signals=["tag", "valid"] ) @@ -93,8 +94,7 @@ class TB(object): user_clk=dut.clk, user_reset=dut.rst, - rq_entity=dut, - rq_name="m_axis_rq", + rq_bus=AxiStreamBus.from_prefix(dut, "m_axis_rq"), pcie_rq_seq_num0=dut.s_axis_rq_seq_num_0, pcie_rq_seq_num_vld0=dut.s_axis_rq_seq_num_valid_0, pcie_rq_seq_num1=dut.s_axis_rq_seq_num_1, @@ -122,8 +122,8 @@ class TB(object): self.dma_ram = PsdpRamRead(dut, "ram", dut.clk, dut.rst, size=2**16) # Control - self.write_desc_source = DescSource(dut, "s_axis_write_desc", dut.clk, dut.rst) - self.write_desc_status_sink = DescStatusSink(dut, "m_axis_write_desc_status", dut.clk, dut.rst) + self.write_desc_source = DescSource(DescBus.from_prefix(dut, "s_axis_write_desc"), dut.clk, dut.rst) + self.write_desc_status_sink = DescStatusSink(DescStatusBus.from_prefix(dut, "m_axis_write_desc_status"), dut.clk, dut.rst) dut.requester_id.setimmediatevalue(0) dut.requester_id_enable.setimmediatevalue(0) diff --git a/tb/pcie_us_axi_dma/test_pcie_us_axi_dma.py b/tb/pcie_us_axi_dma/test_pcie_us_axi_dma.py index 7e77ff2..d08f349 100644 --- a/tb/pcie_us_axi_dma/test_pcie_us_axi_dma.py +++ b/tb/pcie_us_axi_dma/test_pcie_us_axi_dma.py @@ -34,17 +34,18 @@ import cocotb from cocotb.triggers import RisingEdge, FallingEdge, Timer from cocotb.regression import TestFactory +from cocotbext.axi import AxiStreamBus from cocotbext.pcie.core import RootComplex from cocotbext.pcie.xilinx.us import UltraScalePlusPcieDevice -from cocotbext.axi import AxiRam +from cocotbext.axi import AxiBus, AxiRam from cocotbext.axi.stream import define_stream from cocotbext.axi.utils import hexdump_str -DescTransaction, DescSource, DescSink, DescMonitor = define_stream("Desc", +DescBus, DescTransaction, DescSource, DescSink, DescMonitor = define_stream("Desc", signals=["pcie_addr", "axi_addr", "len", "tag", "valid", "ready"] ) -DescStatusTransaction, DescStatusSource, DescStatusSink, DescStatusMonitor = define_stream("DescStatus", +DescStatusBus, DescStatusTransaction, DescStatusSource, DescStatusSink, DescStatusMonitor = define_stream("DescStatus", signals=["tag", "valid"] ) @@ -83,15 +84,13 @@ class TB(object): user_clk=dut.clk, user_reset=dut.rst, - rq_entity=dut, - rq_name="m_axis_rq", + rq_bus=AxiStreamBus.from_prefix(dut, "m_axis_rq"), pcie_rq_seq_num0=dut.s_axis_rq_seq_num_0, pcie_rq_seq_num_vld0=dut.s_axis_rq_seq_num_valid_0, pcie_rq_seq_num1=dut.s_axis_rq_seq_num_1, pcie_rq_seq_num_vld1=dut.s_axis_rq_seq_num_valid_1, - rc_entity=dut, - rc_name="s_axis_rc", + rc_bus=AxiStreamBus.from_prefix(dut, "s_axis_rc"), cfg_max_payload=dut.max_payload_size, cfg_max_read_req=dut.max_read_request_size, @@ -107,14 +106,14 @@ class TB(object): self.rc.make_port().connect(self.dev) # AXI - self.axi_ram = AxiRam(dut, "m_axi", dut.clk, dut.rst, size=2**16) + self.axi_ram = AxiRam(AxiBus.from_prefix(dut, "m_axi"), dut.clk, dut.rst, size=2**16) # Control - self.read_desc_source = DescSource(dut, "s_axis_read_desc", dut.clk, dut.rst) - self.read_desc_status_sink = DescStatusSink(dut, "m_axis_read_desc_status", dut.clk, dut.rst) + self.read_desc_source = DescSource(DescBus.from_prefix(dut, "s_axis_read_desc"), dut.clk, dut.rst) + self.read_desc_status_sink = DescStatusSink(DescStatusBus.from_prefix(dut, "m_axis_read_desc_status"), dut.clk, dut.rst) - self.write_desc_source = DescSource(dut, "s_axis_write_desc", dut.clk, dut.rst) - self.write_desc_status_sink = DescStatusSink(dut, "m_axis_write_desc_status", dut.clk, dut.rst) + self.write_desc_source = DescSource(DescBus.from_prefix(dut, "s_axis_write_desc"), dut.clk, dut.rst) + self.write_desc_status_sink = DescStatusSink(DescStatusBus.from_prefix(dut, "m_axis_write_desc_status"), dut.clk, dut.rst) dut.requester_id.setimmediatevalue(0) dut.requester_id_enable.setimmediatevalue(0) diff --git a/tb/pcie_us_axi_dma_rd/test_pcie_us_axi_dma_rd.py b/tb/pcie_us_axi_dma_rd/test_pcie_us_axi_dma_rd.py index 85c1867..2fc16cc 100644 --- a/tb/pcie_us_axi_dma_rd/test_pcie_us_axi_dma_rd.py +++ b/tb/pcie_us_axi_dma_rd/test_pcie_us_axi_dma_rd.py @@ -34,17 +34,18 @@ import cocotb from cocotb.triggers import RisingEdge, FallingEdge, Timer from cocotb.regression import TestFactory +from cocotbext.axi import AxiStreamBus from cocotbext.pcie.core import RootComplex from cocotbext.pcie.xilinx.us import UltraScalePlusPcieDevice -from cocotbext.axi import AxiRamWrite +from cocotbext.axi import AxiWriteBus, AxiRamWrite from cocotbext.axi.stream import define_stream from cocotbext.axi.utils import hexdump_str -DescTransaction, DescSource, DescSink, DescMonitor = define_stream("Desc", +DescBus, DescTransaction, DescSource, DescSink, DescMonitor = define_stream("Desc", signals=["pcie_addr", "axi_addr", "len", "tag", "valid", "ready"] ) -DescStatusTransaction, DescStatusSource, DescStatusSink, DescStatusMonitor = define_stream("DescStatus", +DescStatusBus, DescStatusTransaction, DescStatusSource, DescStatusSink, DescStatusMonitor = define_stream("DescStatus", signals=["tag", "valid"] ) @@ -83,15 +84,13 @@ class TB(object): user_clk=dut.clk, user_reset=dut.rst, - rq_entity=dut, - rq_name="m_axis_rq", + rq_bus=AxiStreamBus.from_prefix(dut, "m_axis_rq"), pcie_rq_seq_num0=dut.s_axis_rq_seq_num_0, pcie_rq_seq_num_vld0=dut.s_axis_rq_seq_num_valid_0, pcie_rq_seq_num1=dut.s_axis_rq_seq_num_1, pcie_rq_seq_num_vld1=dut.s_axis_rq_seq_num_valid_1, - rc_entity=dut, - rc_name="s_axis_rc", + rc_bus=AxiStreamBus.from_prefix(dut, "s_axis_rc"), cfg_max_read_req=dut.max_read_request_size, @@ -104,11 +103,11 @@ class TB(object): self.rc.make_port().connect(self.dev) # AXI - self.axi_ram = AxiRamWrite(dut, "m_axi", dut.clk, dut.rst, size=2**16) + self.axi_ram = AxiRamWrite(AxiWriteBus.from_prefix(dut, "m_axi"), dut.clk, dut.rst, size=2**16) # Control - self.read_desc_source = DescSource(dut, "s_axis_read_desc", dut.clk, dut.rst) - self.read_desc_status_sink = DescStatusSink(dut, "m_axis_read_desc_status", dut.clk, dut.rst) + self.read_desc_source = DescSource(DescBus.from_prefix(dut, "s_axis_read_desc"), dut.clk, dut.rst) + self.read_desc_status_sink = DescStatusSink(DescStatusBus.from_prefix(dut, "m_axis_read_desc_status"), dut.clk, dut.rst) dut.requester_id.setimmediatevalue(0) dut.requester_id_enable.setimmediatevalue(0) diff --git a/tb/pcie_us_axi_dma_wr/test_pcie_us_axi_dma_wr.py b/tb/pcie_us_axi_dma_wr/test_pcie_us_axi_dma_wr.py index f2b8841..dd643f5 100644 --- a/tb/pcie_us_axi_dma_wr/test_pcie_us_axi_dma_wr.py +++ b/tb/pcie_us_axi_dma_wr/test_pcie_us_axi_dma_wr.py @@ -34,17 +34,18 @@ import cocotb from cocotb.triggers import RisingEdge, FallingEdge, Timer from cocotb.regression import TestFactory +from cocotbext.axi import AxiStreamBus from cocotbext.pcie.core import RootComplex from cocotbext.pcie.xilinx.us import UltraScalePlusPcieDevice -from cocotbext.axi import AxiRamRead +from cocotbext.axi import AxiReadBus, AxiRamRead from cocotbext.axi.stream import define_stream from cocotbext.axi.utils import hexdump_str -DescTransaction, DescSource, DescSink, DescMonitor = define_stream("Desc", +DescBus, DescTransaction, DescSource, DescSink, DescMonitor = define_stream("Desc", signals=["pcie_addr", "axi_addr", "len", "tag", "valid", "ready"] ) -DescStatusTransaction, DescStatusSource, DescStatusSink, DescStatusMonitor = define_stream("DescStatus", +DescStatusBus, DescStatusTransaction, DescStatusSource, DescStatusSink, DescStatusMonitor = define_stream("DescStatus", signals=["tag", "valid"] ) @@ -83,8 +84,7 @@ class TB(object): user_clk=dut.clk, user_reset=dut.rst, - rq_entity=dut, - rq_name="m_axis_rq", + rq_bus=AxiStreamBus.from_prefix(dut, "m_axis_rq"), pcie_rq_seq_num0=dut.s_axis_rq_seq_num_0, pcie_rq_seq_num_vld0=dut.s_axis_rq_seq_num_valid_0, pcie_rq_seq_num1=dut.s_axis_rq_seq_num_1, @@ -109,11 +109,11 @@ class TB(object): dut.s_axis_rq_tvalid.setimmediatevalue(0) # AXI - self.axi_ram = AxiRamRead(dut, "m_axi", dut.clk, dut.rst, size=2**16) + self.axi_ram = AxiRamRead(AxiReadBus.from_prefix(dut, "m_axi"), dut.clk, dut.rst, size=2**16) # Control - self.write_desc_source = DescSource(dut, "s_axis_write_desc", dut.clk, dut.rst) - self.write_desc_status_sink = DescStatusSink(dut, "m_axis_write_desc_status", dut.clk, dut.rst) + self.write_desc_source = DescSource(DescBus.from_prefix(dut, "s_axis_write_desc"), dut.clk, dut.rst) + self.write_desc_status_sink = DescStatusSink(DescStatusBus.from_prefix(dut, "m_axis_write_desc_status"), dut.clk, dut.rst) dut.requester_id.setimmediatevalue(0) dut.requester_id_enable.setimmediatevalue(0) diff --git a/tb/pcie_us_axi_master/test_pcie_us_axi_master.py b/tb/pcie_us_axi_master/test_pcie_us_axi_master.py index 51daa92..493ce2c 100644 --- a/tb/pcie_us_axi_master/test_pcie_us_axi_master.py +++ b/tb/pcie_us_axi_master/test_pcie_us_axi_master.py @@ -36,9 +36,10 @@ import cocotb from cocotb.triggers import RisingEdge, FallingEdge, Timer from cocotb.regression import TestFactory +from cocotbext.axi import AxiStreamBus from cocotbext.pcie.core import RootComplex from cocotbext.pcie.xilinx.us import UltraScalePlusPcieDevice -from cocotbext.axi import AxiRam +from cocotbext.axi import AxiBus, AxiRam @contextmanager @@ -88,11 +89,9 @@ class TB(object): user_clk=dut.clk, user_reset=dut.rst, - cq_entity=dut, - cq_name="s_axis_cq", + cq_bus=AxiStreamBus.from_prefix(dut, "s_axis_cq"), - cc_entity=dut, - cc_name="m_axis_cc", + cc_bus=AxiStreamBus.from_prefix(dut, "m_axis_cc"), cfg_max_payload=dut.max_payload_size, ) @@ -105,7 +104,7 @@ class TB(object): self.rc.make_port().connect(self.dev) # AXI - self.axi_ram = AxiRam(dut, "m_axi", dut.clk, dut.rst, size=2**16) + self.axi_ram = AxiRam(AxiBus.from_prefix(dut, "m_axi"), dut.clk, dut.rst, size=2**16) dut.completer_id.setimmediatevalue(0) dut.completer_id_enable.setimmediatevalue(0) diff --git a/tb/pcie_us_axi_master_rd/test_pcie_us_axi_master_rd.py b/tb/pcie_us_axi_master_rd/test_pcie_us_axi_master_rd.py index 201f4fd..142336a 100644 --- a/tb/pcie_us_axi_master_rd/test_pcie_us_axi_master_rd.py +++ b/tb/pcie_us_axi_master_rd/test_pcie_us_axi_master_rd.py @@ -36,9 +36,10 @@ import cocotb from cocotb.triggers import RisingEdge, FallingEdge, Timer from cocotb.regression import TestFactory +from cocotbext.axi import AxiStreamBus from cocotbext.pcie.core import RootComplex from cocotbext.pcie.xilinx.us import UltraScalePlusPcieDevice -from cocotbext.axi import AxiRamRead +from cocotbext.axi import AxiReadBus, AxiRamRead @contextmanager @@ -88,11 +89,9 @@ class TB(object): user_clk=dut.clk, user_reset=dut.rst, - cq_entity=dut, - cq_name="s_axis_cq", + cq_bus=AxiStreamBus.from_prefix(dut, "s_axis_cq"), - cc_entity=dut, - cc_name="m_axis_cc", + cc_bus=AxiStreamBus.from_prefix(dut, "m_axis_cc"), cfg_max_payload=dut.max_payload_size, ) @@ -105,7 +104,7 @@ class TB(object): self.rc.make_port().connect(self.dev) # AXI - self.axi_ram = AxiRamRead(dut, "m_axi", dut.clk, dut.rst, size=2**16) + self.axi_ram = AxiRamRead(AxiReadBus.from_prefix(dut, "m_axi"), dut.clk, dut.rst, size=2**16) dut.completer_id.setimmediatevalue(0) dut.completer_id_enable.setimmediatevalue(0) diff --git a/tb/pcie_us_axi_master_wr/test_pcie_us_axi_master_wr.py b/tb/pcie_us_axi_master_wr/test_pcie_us_axi_master_wr.py index e20ad01..c7d3601 100644 --- a/tb/pcie_us_axi_master_wr/test_pcie_us_axi_master_wr.py +++ b/tb/pcie_us_axi_master_wr/test_pcie_us_axi_master_wr.py @@ -36,9 +36,10 @@ import cocotb from cocotb.triggers import RisingEdge, FallingEdge, Timer from cocotb.regression import TestFactory +from cocotbext.axi import AxiStreamBus from cocotbext.pcie.core import RootComplex from cocotbext.pcie.xilinx.us import UltraScalePlusPcieDevice -from cocotbext.axi import AxiRamWrite +from cocotbext.axi import AxiWriteBus, AxiRamWrite @contextmanager @@ -88,8 +89,7 @@ class TB(object): user_clk=dut.clk, user_reset=dut.rst, - cq_entity=dut, - cq_name="s_axis_cq", + cq_bus=AxiStreamBus.from_prefix(dut, "s_axis_cq") ) self.dev.log.setLevel(logging.DEBUG) @@ -100,7 +100,7 @@ class TB(object): self.rc.make_port().connect(self.dev) # AXI - self.axi_ram = AxiRamWrite(dut, "m_axi", dut.clk, dut.rst, size=2**16) + self.axi_ram = AxiRamWrite(AxiWriteBus.from_prefix(dut, "m_axi"), dut.clk, dut.rst, size=2**16) # monitor error outputs self.status_error_uncor_asserted = False diff --git a/tb/pcie_us_axil_master/test_pcie_us_axil_master.py b/tb/pcie_us_axil_master/test_pcie_us_axil_master.py index 2ff8897..a87e3ad 100644 --- a/tb/pcie_us_axil_master/test_pcie_us_axil_master.py +++ b/tb/pcie_us_axil_master/test_pcie_us_axil_master.py @@ -36,9 +36,10 @@ import cocotb from cocotb.triggers import RisingEdge, FallingEdge, Timer from cocotb.regression import TestFactory +from cocotbext.axi import AxiStreamBus from cocotbext.pcie.core import RootComplex from cocotbext.pcie.xilinx.us import UltraScalePlusPcieDevice -from cocotbext.axi import AxiLiteRam +from cocotbext.axi import AxiLiteBus, AxiLiteRam @contextmanager @@ -88,11 +89,9 @@ class TB(object): user_clk=dut.clk, user_reset=dut.rst, - cq_entity=dut, - cq_name="s_axis_cq", + cq_bus=AxiStreamBus.from_prefix(dut, "s_axis_cq"), - cc_entity=dut, - cc_name="m_axis_cc", + cc_bus=AxiStreamBus.from_prefix(dut, "m_axis_cc") ) self.dev.log.setLevel(logging.DEBUG) @@ -103,7 +102,7 @@ class TB(object): self.rc.make_port().connect(self.dev) # AXI - self.axil_ram = AxiLiteRam(dut, "m_axil", dut.clk, dut.rst, size=2**16) + self.axil_ram = AxiLiteRam(AxiLiteBus.from_prefix(dut, "m_axil"), dut.clk, dut.rst, size=2**16) dut.completer_id.setimmediatevalue(0) dut.completer_id_enable.setimmediatevalue(0)