FPGA/verilog-pcie
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yield config_read and config_write

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This commit is contained in:
Alex Forencich 2018-10-14 23:59:03 -07:00
parent 9f4e62333a
commit cbd1577129
1 changed files with 3 additions and 2 deletions
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5
tb/pcie.py
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@ -3471,7 +3471,8 @@ class RootComplex(Switch):
if not offset:
raise Exception("Capability not found")
return self.config_read(dev, addr+offset, length, timeout)
val = yield from self.config_read(dev, addr+offset, length, timeout)
return val
def capability_write(self, dev, cap_id, addr, data, timeout=0):
ti = self.tree.find_dev(dev)
@ -3488,7 +3489,7 @@ class RootComplex(Switch):
if not offset:
raise Exception("Capability not found")
self.config_write(dev, addr+offset, data, timeout)
yield self.config_write(dev, addr+offset, data, timeout)
def io_read(self, addr, length, timeout=0):
n = 0