Add some more comments
This commit is contained in:
Alex Forencich
parent
24f709573c
commit
d81ee9487a
@ -341,6 +341,7 @@ always @* begin
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s_axis_cq_tready_next = !tlp_cmd_valid_reg;
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if (s_axis_cq_tready & s_axis_cq_tvalid) begin
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// header fields
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tlp_cmd_at_next = s_axis_cq_tdata[1:0];
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pcie_addr_next = {s_axis_cq_tdata[63:2], first_be_offset};
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tlp_cmd_status_next = CPL_STATUS_SC; // successful completion
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@ -357,10 +358,12 @@ always @* begin
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tlp_cmd_attr_next = s_axis_cq_tdata[126:124];
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end
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// tuser fields
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first_be_next = s_axis_cq_tuser[3:0];
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last_be_next = s_axis_cq_tuser[7:4];
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if (AXIS_PCIE_DATA_WIDTH == 64) begin
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// 64 bit interface hasn't processed the whole header yet
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s_axis_cq_tready_next = 1'b1;
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if (s_axis_cq_tlast) begin
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// truncated packet
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@ -371,6 +374,7 @@ always @* begin
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axi_state_next = AXI_STATE_HEADER;
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end
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end else begin
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// processed whole header; check request type
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if (s_axis_cq_tdata[78:75] == REQ_MEM_READ) begin
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// read request
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s_axis_cq_tready_next = 1'b0;
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@ -403,7 +407,7 @@ always @* begin
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end
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end
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AXI_STATE_HEADER: begin
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// header state, store rest of header
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// header state, store rest of header (64 bit interface only)
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s_axis_cq_tready_next = 1'b1;
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if (s_axis_cq_tready & s_axis_cq_tvalid) begin
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@ -419,6 +423,7 @@ always @* begin
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tlp_cmd_tc_next = s_axis_cq_tdata[59:57];
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tlp_cmd_attr_next = s_axis_cq_tdata[62:60];
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// processed whole header; check request type
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if (s_axis_cq_tdata[14:11] == REQ_MEM_READ) begin
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// read request
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s_axis_cq_tready_next = 1'b0;
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@ -463,10 +468,13 @@ always @* begin
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tlp_dword_count_next = max_payload_size_dw_reg - pcie_addr_reg[6:2];
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end
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// read completion TLP will transfer DWORD count minus offset into first DWORD
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op_count_next = op_count_reg - (tlp_dword_count_next << 2) + pcie_addr_reg[1:0];
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op_dword_count_next = op_dword_count_reg - tlp_dword_count_next;
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// number of bus transfers from AXI, DWORD count plus DWORD offset, divided by bus width in DWORDS
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tlp_cmd_input_cycle_len_next = (tlp_dword_count_next + pcie_addr_reg[OFFSET_WIDTH+2-1:2] - 1) >> (AXI_BURST_SIZE-2);
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// number of bus transfers in TLP, DOWRD count plus payload start DWORD offset, divided by bus width in DWORDS
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if (AXIS_PCIE_DATA_WIDTH == 64) begin
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tlp_cmd_output_cycle_len_next = (tlp_dword_count_next + 1 - 1) >> (AXI_BURST_SIZE-2);
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end else begin
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@ -476,6 +484,8 @@ always @* begin
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tlp_cmd_addr_next = pcie_addr_reg;
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tlp_cmd_byte_len_next = op_count_reg;
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tlp_cmd_dword_len_next = tlp_dword_count_next;
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// required DWORD shift to place first DWORD read from AXI into proper position in payload
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// bubble cycle required if first AXI transfer does not fill first payload transfer
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if (AXIS_PCIE_DATA_WIDTH == 64) begin
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tlp_cmd_offset_next = 1-pcie_addr_reg[OFFSET_WIDTH+2-1:2];
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tlp_cmd_bubble_cycle_next = 1'b0;
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@ -509,8 +519,11 @@ always @* begin
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m_axi_arlen_next = (tr_dword_count_next - 1) >> (AXI_BURST_SIZE-2);
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end
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// increment address by transfer size
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pcie_addr_next = pcie_addr_reg + (tr_dword_count_next << 2);
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// first transfer will end on DWORD boundary, so subsequent transfers will be DWORD aligned
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pcie_addr_next[1:0] = 2'b0;
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// keep track of how much more needs to be read to fill the TLP
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tlp_dword_count_next = tlp_dword_count_reg - tr_dword_count_next;
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if (tlp_dword_count_next > 0) begin
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@ -611,6 +624,7 @@ always @* begin
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// idle state, wait for command
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m_axi_rready_next = 1'b0;
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// store TLP fields and transfer parameters
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at_next = tlp_cmd_at_reg;
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tlp_addr_next = tlp_cmd_addr_reg;
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tlp_len_next = tlp_cmd_byte_len_reg;
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@ -631,6 +645,7 @@ always @* begin
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if (tlp_cmd_valid_reg) begin
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tlp_cmd_ready = 1'b1;
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if (status_next == CPL_STATUS_SC) begin
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// SC status, output TLP header
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if (AXIS_PCIE_DATA_WIDTH == 64) begin
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m_axi_rready_next = 1'b0;
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end else begin
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@ -638,6 +653,7 @@ always @* begin
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end
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tlp_state_next = TLP_STATE_HEADER_1;
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end else begin
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// status other than SC
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tlp_state_next = TLP_STATE_CPL_1;
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end
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end else begin
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@ -650,6 +666,7 @@ always @* begin
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m_axi_rready_next = 1'b0;
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if (m_axis_cc_tready_int_reg) begin
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// output first part of header
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m_axis_cc_tvalid_int = 1'b1;
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m_axi_rready_next = m_axis_cc_tready_int_early;
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@ -674,11 +691,13 @@ always @* begin
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m_axi_rready_next = m_axis_cc_tready_int_early && input_active_next;
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tlp_state_next = TLP_STATE_HEADER_1;
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end else begin
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// some data is transferred with header
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if (AXIS_PCIE_DATA_WIDTH == 256) begin
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dword_count_next = dword_count_reg - 5;
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end else begin
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dword_count_next = dword_count_reg - 1;
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end
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// update cycle counters
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if (input_active_reg) begin
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input_cycle_count_next = input_cycle_count_reg - 1;
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input_active_next = input_cycle_count_reg > 0;
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@ -686,12 +705,14 @@ always @* begin
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output_cycle_count_next = output_cycle_count_reg - 1;
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last_cycle_next = output_cycle_count_next == 0;
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// transfer data
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if (AXIS_PCIE_DATA_WIDTH == 256) begin
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m_axis_cc_tdata_int[255:96] = shift_axi_rdata[255:96];
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end else begin
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m_axis_cc_tdata_int[127:96] = shift_axi_rdata[127:96];
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end
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// generate tvalid and tkeep signals for header and data
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m_axis_cc_tvalid_int = 1'b1;
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if (AXIS_PCIE_DATA_WIDTH == 256) begin
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if (dword_count_reg >= 5) begin
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@ -824,6 +845,7 @@ always @* begin
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transfer_in_save = 1'b1;
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if (bubble_cycle_reg) begin
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// bubble cycle; store input data and update input cycle count
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if (input_active_reg) begin
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input_cycle_count_next = input_cycle_count_reg - 1;
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input_active_next = input_cycle_count_reg > 0;
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@ -832,7 +854,9 @@ always @* begin
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m_axi_rready_next = m_axis_cc_tready_int_early && input_active_next;
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tlp_state_next = TLP_STATE_TRANSFER;
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end else begin
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// update DWORD count
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dword_count_next = dword_count_reg - AXI_STRB_WIDTH/4;
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// update cycle counters
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if (input_active_reg) begin
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input_cycle_count_next = input_cycle_count_reg - 1;
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input_active_next = input_cycle_count_reg > 0;
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@ -840,6 +864,7 @@ always @* begin
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output_cycle_count_next = output_cycle_count_reg - 1;
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last_cycle_next = output_cycle_count_next == 0;
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// output data and generate tvalid and tkeep signals
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m_axis_cc_tdata_int = shift_axi_rdata;
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m_axis_cc_tvalid_int = 1'b1;
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if (dword_count_reg >= AXI_STRB_WIDTH/4) begin
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@ -897,6 +922,7 @@ always @* begin
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m_axis_cc_tdata_int[42:32] = 11'd0; // DWORD count
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m_axis_cc_tdata_int[45:43] = status_reg;
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// generate tvalid and tkeep signals for completion
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if (AXIS_PCIE_DATA_WIDTH == 256) begin
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m_axis_cc_tkeep_int = 8'b00000111;
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m_axis_cc_tlast_int = 1'b1;
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@ -269,6 +269,8 @@ always @* begin
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m_axi_awaddr_next = axi_addr_next;
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// required DWORD shift to place first DWORD from the TLP payload into proper position on AXI interface
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// bubble cycle required if first TLP payload transfer does not fill first AXI transfer
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if (AXIS_PCIE_DATA_WIDTH == 256) begin
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offset_next = axi_addr_next[OFFSET_WIDTH+2-1:2] - 4;
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bubble_cycle_next = axi_addr_next[OFFSET_WIDTH+2-1:2] < 4;
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@ -278,11 +280,13 @@ always @* begin
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end
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first_cycle_next = 1'b1;
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// number of bus transfers in TLP, DOWRD count plus payload start DWORD offset, divided by bus width in DWORDS
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if (AXIS_PCIE_DATA_WIDTH == 256) begin
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input_cycle_count_next = (tr_dword_count_next + 4 - 1) >> (AXI_BURST_SIZE-2);
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end else begin
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input_cycle_count_next = (tr_dword_count_next - 1) >> (AXI_BURST_SIZE-2);
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end
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// number of bus transfers to AXI, DWORD count plus DWORD offset, divided by bus width in DWORDS
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output_cycle_count_next = (tr_dword_count_next + axi_addr_next[OFFSET_WIDTH+2-1:2] - 1) >> (AXI_BURST_SIZE-2);
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last_cycle_next = output_cycle_count_next == 0;
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input_active_next = 1'b1;
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@ -291,6 +295,7 @@ always @* begin
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// write request
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m_axi_awvalid_next = 1'b1;
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if (AXIS_PCIE_DATA_WIDTH == 256) begin
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// some data is transferred with header
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input_active_next = input_cycle_count_next > 0;
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input_cycle_count_next = input_cycle_count_next - 1;
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s_axis_cq_tready_next = 1'b0;
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@ -330,7 +335,7 @@ always @* begin
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end
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end
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STATE_HEADER: begin
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// header state, store rest of header
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// header state, store rest of header (64 bit interface only)
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s_axis_cq_tready_next = m_axi_wready_int_early;
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if (s_axis_cq_tready && s_axis_cq_tvalid) begin
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@ -359,11 +364,15 @@ always @* begin
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m_axi_awaddr_next = axi_addr_reg;
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// required DWORD shift to place first DWORD from the TLP payload into proper position on AXI interface
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// bubble cycle required if first TLP payload transfer does not fill first AXI transfer
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offset_next = axi_addr_reg[OFFSET_WIDTH+2-1:2];
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bubble_cycle_next = 1'b0;
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first_cycle_next = 1'b1;
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// number of bus transfers in TLP, DOWRD count plus payload start DWORD offset, divided by bus width in DWORDS
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input_cycle_count_next = (tr_dword_count_next - 1) >> (AXI_BURST_SIZE-2);
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// number of bus transfers to AXI, DWORD count plus DWORD offset, divided by bus width in DWORDS
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output_cycle_count_next = (tr_dword_count_next + axi_addr_reg[OFFSET_WIDTH+2-1:2] - 1) >> (AXI_BURST_SIZE-2);
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last_cycle_next = output_cycle_count_next == 0;
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input_active_next = 1'b1;
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@ -394,21 +403,25 @@ always @* begin
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if (m_axi_wready_int_reg && ((s_axis_cq_tready && s_axis_cq_tvalid) || !input_active_reg || (AXIS_PCIE_DATA_WIDTH == 256 && first_cycle_reg && !bubble_cycle_reg))) begin
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transfer_in_save = s_axis_cq_tready && s_axis_cq_tvalid;
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// transfer data
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if (AXIS_PCIE_DATA_WIDTH == 256 && first_cycle_reg && !bubble_cycle_reg) begin
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m_axi_wdata_int = {save_axis_tdata_reg, {AXIS_PCIE_DATA_WIDTH{1'b0}}} >> ((AXI_STRB_WIDTH/4-offset_reg)*32);
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s_axis_cq_tready_next = m_axi_wready_int_early && input_active_reg;
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end else begin
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m_axi_wdata_int = shift_axis_tdata;
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end
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// generate strb signal
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if (first_cycle_reg) begin
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m_axi_wstrb_int = {{AXI_STRB_WIDTH-4{1'b1}}, first_be_reg} << (axi_addr_reg[OFFSET_WIDTH+2-1:2]*4);
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end else begin
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m_axi_wstrb_int = {AXI_STRB_WIDTH{1'b1}};
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end
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// update address and length counters
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axi_addr_next = axi_addr_reg + (AXI_STRB_WIDTH/4 - axi_addr_reg[OFFSET_WIDTH+2-1:2])*4;
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tr_dword_count_next = tr_dword_count_reg - (AXI_STRB_WIDTH/4 - axi_addr_reg[OFFSET_WIDTH+2-1:2]);
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op_dword_count_next = op_dword_count_reg - (AXI_STRB_WIDTH/4 - axi_addr_reg[OFFSET_WIDTH+2-1:2]);
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// update cycle counters
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if (input_active_reg && !(AXIS_PCIE_DATA_WIDTH == 256 && first_cycle_reg && !bubble_cycle_reg)) begin
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input_cycle_count_next = input_cycle_count_reg - 1;
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input_active_next = input_cycle_count_reg > 0;
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@ -416,6 +429,7 @@ always @* begin
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output_cycle_count_next = output_cycle_count_reg - 1;
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last_cycle_next = output_cycle_count_next == 0;
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// modify strb signal at end of transfer
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if (last_cycle_reg) begin
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m_axi_wstrb_int = m_axi_wstrb_int & {last_be_reg, {AXI_STRB_WIDTH-4{1'b1}}} >> (AXI_STRB_WIDTH-(tr_dword_count_reg+axi_addr_reg[OFFSET_WIDTH+2-1:2])*4);
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m_axi_wlast_int = 1'b1;
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