From f567db764bdedcbfbffa957b480be5cbb4d37e39 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Wed, 11 Nov 2020 23:54:39 -0800 Subject: [PATCH] Rewrite 4K address boundary crossing checks --- rtl/dma_if_pcie_us_rd.v | 9 +++------ rtl/dma_if_pcie_us_wr.v | 11 ++++------- rtl/pcie_us_axi_dma_rd.v | 18 +++++++----------- rtl/pcie_us_axi_dma_wr.v | 20 ++++++-------------- 4 files changed, 20 insertions(+), 38 deletions(-) diff --git a/rtl/dma_if_pcie_us_rd.v b/rtl/dma_if_pcie_us_rd.v index 0e3e090..8172001 100644 --- a/rtl/dma_if_pcie_us_rd.v +++ b/rtl/dma_if_pcie_us_rd.v @@ -402,9 +402,6 @@ assign m_axis_read_desc_status_valid = m_axis_read_desc_status_valid_reg; assign status_error_cor = status_error_cor_reg; assign status_error_uncor = status_error_uncor_reg; -wire [PCIE_ADDR_WIDTH-1:0] req_pcie_addr_plus_max_read_request = req_pcie_addr_reg + {max_read_request_size_dw_reg, 2'b00}; -wire [PCIE_ADDR_WIDTH-1:0] req_pcie_addr_plus_op_count = req_pcie_addr_reg + req_op_count_reg; - // PCIe tag management wire [PCIE_TAG_WIDTH-1:0] new_tag; wire new_tag_valid; @@ -584,11 +581,11 @@ always @* begin // TLP size computation if (req_op_count_reg + req_pcie_addr_reg[1:0] <= {max_read_request_size_dw_reg, 2'b00}) begin // packet smaller than max read request size - if (req_pcie_addr_reg[12] != req_pcie_addr_plus_op_count[12]) begin + if (((req_pcie_addr_reg & 12'hfff) + (req_op_count_reg & 12'hfff)) >> 12 != 0 || req_op_count_reg >> 12 != 0) begin // crosses 4k boundary req_tlp_count_next = 13'h1000 - req_pcie_addr_reg[11:0]; dword_count = 11'h400 - req_pcie_addr_reg[11:2]; - req_last_tlp = req_pcie_addr_plus_op_count[11:0] == 0; + req_last_tlp = (((req_pcie_addr_reg & 12'hfff) + (req_op_count_reg & 12'hfff)) & 12'hfff) == 0; // optimized req_pcie_addr = req_addr_reg + req_tlp_count_next req_pcie_addr[PCIE_ADDR_WIDTH-1:12] = req_pcie_addr_reg[PCIE_ADDR_WIDTH-1:12]+1; req_pcie_addr[11:0] = 12'd0; @@ -603,7 +600,7 @@ always @* begin end end else begin // packet larger than max read request size - if (req_pcie_addr_reg[12] != req_pcie_addr_plus_max_read_request[12]) begin + if (((req_pcie_addr_reg & 12'hfff) + {max_read_request_size_dw_reg, 2'b00}) >> 12 != 0) begin // crosses 4k boundary req_tlp_count_next = 13'h1000 - req_pcie_addr_reg[11:0]; dword_count = 11'h400 - req_pcie_addr_reg[11:2]; diff --git a/rtl/dma_if_pcie_us_wr.v b/rtl/dma_if_pcie_us_wr.v index 70ab186..6ee660a 100644 --- a/rtl/dma_if_pcie_us_wr.v +++ b/rtl/dma_if_pcie_us_wr.v @@ -384,9 +384,6 @@ assign ram_rd_cmd_addr = ram_rd_cmd_addr_reg; assign ram_rd_cmd_valid = ram_rd_cmd_valid_reg; assign ram_rd_resp_ready = ram_rd_resp_ready_cmb; -wire [PCIE_ADDR_WIDTH-1:0] pcie_addr_plus_max_payload = pcie_addr_reg + {max_payload_size_dw_reg, 2'b00}; -wire [PCIE_ADDR_WIDTH-1:0] pcie_addr_plus_op_count = pcie_addr_reg + op_count_reg; - // operation tag management reg [OP_TAG_WIDTH+1-1:0] op_table_start_ptr_reg = 0; reg [PCIE_ADDR_WIDTH-1:0] op_table_start_pcie_addr; @@ -476,7 +473,7 @@ always @* begin if (op_count_next <= {max_payload_size_dw_reg, 2'b00}-pcie_addr_next[1:0]) begin // packet smaller than max payload size - if ((pcie_addr_next ^ (pcie_addr_next + op_count_next)) & (1 << 12)) begin + if (((pcie_addr_next & 12'hfff) + (op_count_next & 12'hfff)) >> 12 != 0 || op_count_next >> 12 != 0) begin // crosses 4k boundary tlp_count_next = 13'h1000 - pcie_addr_next[11:0]; end else begin @@ -485,7 +482,7 @@ always @* begin end end else begin // packet larger than max payload size - if ((pcie_addr_next ^ (pcie_addr_next + {max_payload_size_dw_reg, 2'b00})) & (1 << 12)) begin + if (((pcie_addr_next & 12'hfff) + {max_payload_size_dw_reg, 2'b00}) >> 12 != 0) begin // crosses 4k boundary tlp_count_next = 13'h1000 - pcie_addr_next[11:0]; end else begin @@ -536,7 +533,7 @@ always @* begin if (op_count_next <= {max_payload_size_dw_reg, 2'b00}-pcie_addr_next[1:0]) begin // packet smaller than max payload size - if ((pcie_addr_next ^ (pcie_addr_next + op_count_next)) & (1 << 12)) begin + if (((pcie_addr_next & 12'hfff) + (op_count_next & 12'hfff)) >> 12 != 0 || op_count_next >> 12 != 0) begin // crosses 4k boundary tlp_count_next = 13'h1000 - pcie_addr_next[11:0]; end else begin @@ -545,7 +542,7 @@ always @* begin end end else begin // packet larger than max payload size - if ((pcie_addr_next ^ (pcie_addr_next + {max_payload_size_dw_reg, 2'b00})) & (1 << 12)) begin + if (((pcie_addr_next & 12'hfff) + {max_payload_size_dw_reg, 2'b00}) >> 12 != 0) begin // crosses 4k boundary tlp_count_next = 13'h1000 - pcie_addr_next[11:0]; end else begin diff --git a/rtl/pcie_us_axi_dma_rd.v b/rtl/pcie_us_axi_dma_rd.v index bd03d5c..9d5ac6a 100644 --- a/rtl/pcie_us_axi_dma_rd.v +++ b/rtl/pcie_us_axi_dma_rd.v @@ -428,10 +428,6 @@ assign m_axi_bready = m_axi_bready_reg; assign status_error_cor = status_error_cor_reg; assign status_error_uncor = status_error_uncor_reg; -wire [PCIE_ADDR_WIDTH-1:0] req_pcie_addr_plus_max_read_request = req_pcie_addr_reg + {max_read_request_size_dw_reg, 2'b00}; -wire [PCIE_ADDR_WIDTH-1:0] req_pcie_addr_plus_op_count = req_pcie_addr_reg + req_op_count_reg; -wire [PCIE_ADDR_WIDTH-1:0] req_pcie_addr_plus_tlp_count = req_pcie_addr_reg + req_tlp_count_reg; - // PCIe tag management wire [PCIE_TAG_WIDTH-1:0] new_tag; wire new_tag_valid; @@ -625,11 +621,11 @@ always @* begin // TLP size computation if (req_op_count_reg + req_pcie_addr_reg[1:0] <= {max_read_request_size_dw_reg, 2'b00}) begin // packet smaller than max read request size - if (req_pcie_addr_reg[12] != req_pcie_addr_plus_op_count[12]) begin + if (((req_pcie_addr_reg & 12'hfff) + (req_op_count_reg & 12'hfff)) >> 12 != 0 || req_op_count_reg >> 12 != 0) begin // crosses 4k boundary req_tlp_count_next = 13'h1000 - req_pcie_addr_reg[11:0]; dword_count = 11'h400 - req_pcie_addr_reg[11:2]; - req_last_tlp = req_pcie_addr_plus_op_count[11:0] == 0; + req_last_tlp = (((req_pcie_addr_reg & 12'hfff) + (req_op_count_reg & 12'hfff)) & 12'hfff) == 0; // optimized req_pcie_addr = req_addr_reg + req_tlp_count_next req_pcie_addr[PCIE_ADDR_WIDTH-1:12] = req_pcie_addr_reg[PCIE_ADDR_WIDTH-1:12]+1; req_pcie_addr[11:0] = 12'd0; @@ -644,7 +640,7 @@ always @* begin end end else begin // packet larger than max read request size - if (req_pcie_addr_reg[12] != req_pcie_addr_plus_max_read_request[12]) begin + if (((req_pcie_addr_reg & 12'hfff) + {max_read_request_size_dw_reg, 2'b00}) >> 12 != 0) begin // crosses 4k boundary req_tlp_count_next = 13'h1000 - req_pcie_addr_reg[11:0]; dword_count = 11'h400 - req_pcie_addr_reg[11:2]; @@ -1119,7 +1115,7 @@ always @* begin // AXI transfer size computation if (op_count_next <= AXI_MAX_BURST_SIZE-axi_addr_next[OFFSET_WIDTH-1:0] || AXI_MAX_BURST_SIZE >= 4096) begin // packet smaller than max burst size - if ((axi_addr_next ^ (axi_addr_next + op_count_next)) & (1 << 12)) begin + if (((axi_addr_next & 12'hfff) + (op_count_next & 12'hfff)) >> 12 != 0 || op_count_next >> 12 != 0) begin // crosses 4k boundary tr_count_next = 13'h1000 - axi_addr_next[11:0]; end else begin @@ -1128,7 +1124,7 @@ always @* begin end end else begin // packet larger than max burst size - if ((axi_addr_next ^ (axi_addr_next + AXI_MAX_BURST_SIZE)) & (1 << 12)) begin + if (((axi_addr_next & 12'hfff) + AXI_MAX_BURST_SIZE) >> 12 != 0) begin // crosses 4k boundary tr_count_next = 13'h1000 - axi_addr_next[11:0]; end else begin @@ -1208,7 +1204,7 @@ always @* begin // AXI transfer size computation if (op_count_next <= AXI_MAX_BURST_SIZE-axi_addr_next[OFFSET_WIDTH-1:0] || AXI_MAX_BURST_SIZE >= 4096) begin // packet smaller than max burst size - if ((axi_addr_next ^ (axi_addr_next + op_count_next)) & (1 << 12)) begin + if (((axi_addr_next & 12'hfff) + (op_count_next & 12'hfff)) >> 12 != 0 || op_count_next >> 12 != 0) begin // crosses 4k boundary tr_count_next = 13'h1000 - axi_addr_next[11:0]; end else begin @@ -1217,7 +1213,7 @@ always @* begin end end else begin // packet larger than max burst size - if ((axi_addr_next ^ (axi_addr_next + AXI_MAX_BURST_SIZE)) & (1 << 12)) begin + if (((axi_addr_next & 12'hfff) + AXI_MAX_BURST_SIZE) >> 12 != 0) begin // crosses 4k boundary tr_count_next = 13'h1000 - axi_addr_next[11:0]; end else begin diff --git a/rtl/pcie_us_axi_dma_wr.v b/rtl/pcie_us_axi_dma_wr.v index 3f3adc5..8c5055b 100644 --- a/rtl/pcie_us_axi_dma_wr.v +++ b/rtl/pcie_us_axi_dma_wr.v @@ -363,14 +363,6 @@ assign m_axi_arprot = 3'b010; assign m_axi_arvalid = m_axi_arvalid_reg; assign m_axi_rready = m_axi_rready_reg; -wire [PCIE_ADDR_WIDTH-1:0] pcie_addr_plus_max_payload = pcie_addr_reg + {max_payload_size_dw_reg, 2'b00}; -wire [PCIE_ADDR_WIDTH-1:0] pcie_addr_plus_op_count = pcie_addr_reg + op_count_reg; -wire [PCIE_ADDR_WIDTH-1:0] pcie_addr_plus_tlp_count = pcie_addr_reg + tlp_count_reg; - -wire [AXI_ADDR_WIDTH-1:0] axi_addr_plus_max_burst = axi_addr_reg + AXI_MAX_BURST_SIZE; -wire [AXI_ADDR_WIDTH-1:0] axi_addr_plus_op_count = axi_addr_reg + op_count_reg; -wire [AXI_ADDR_WIDTH-1:0] axi_addr_plus_tlp_count = axi_addr_reg + tlp_count_reg; - // operation tag management reg [OP_TAG_WIDTH+1-1:0] op_table_start_ptr_reg = 0; reg [PCIE_ADDR_WIDTH-1:0] op_table_start_pcie_addr; @@ -439,11 +431,11 @@ always @* begin // TLP size computation if (op_count_reg <= {max_payload_size_dw_reg, 2'b00}-pcie_addr_reg[1:0]) begin // packet smaller than max read request size - if (pcie_addr_reg[12] != pcie_addr_plus_op_count[12]) begin + if (((pcie_addr_reg & 12'hfff) + (op_count_reg & 12'hfff)) >> 12 != 0 || op_count_reg >> 12 != 0) begin // crosses 4k boundary tlp_count = 13'h1000 - pcie_addr_reg[11:0]; dword_count = 11'h400 - pcie_addr_reg[11:2]; - last_tlp = pcie_addr_plus_op_count[11:0] == 0; + last_tlp = (((pcie_addr_reg & 12'hfff) + (op_count_reg & 12'hfff)) & 12'hfff) == 0; // optimized pcie_addr = pcie_addr_reg + tlp_count pcie_addr[PCIE_ADDR_WIDTH-1:12] = pcie_addr_reg[PCIE_ADDR_WIDTH-1:12]+1; pcie_addr[11:0] = 12'd0; @@ -458,7 +450,7 @@ always @* begin end end else begin // packet larger than max read request size - if (pcie_addr_reg[12] != pcie_addr_plus_max_payload[12]) begin + if (((pcie_addr_reg & 12'hfff) + {max_payload_size_dw_reg, 2'b00}) >> 12 != 0) begin // crosses 4k boundary tlp_count = 13'h1000 - pcie_addr_reg[11:0]; dword_count = 11'h400 - pcie_addr_reg[11:2]; @@ -480,10 +472,10 @@ always @* begin // AXI transfer size computation if (tlp_count_reg <= AXI_MAX_BURST_SIZE-axi_addr_reg[OFFSET_WIDTH-1:0] || AXI_MAX_BURST_SIZE >= 4096) begin // packet smaller than max read request size - if (axi_addr_reg[12] != axi_addr_plus_tlp_count[12]) begin + if (((axi_addr_reg & 12'hfff) + (tlp_count_reg & 12'hfff)) >> 12 != 0 || tlp_count_reg >> 12 != 0) begin // crosses 4k boundary tr_count = 13'h1000 - axi_addr_reg[11:0]; - last_tr = axi_addr_plus_tlp_count[11:0] == 0; + last_tr = (((axi_addr_reg & 12'hfff) + (tlp_count_reg & 12'hfff)) & 12'hfff) == 0; // optimized axi_addr = axi_addr_reg + tr_count axi_addr[AXI_ADDR_WIDTH-1:12] = axi_addr_reg[AXI_ADDR_WIDTH-1:12]+1; axi_addr[11:0] = 12'd0; @@ -497,7 +489,7 @@ always @* begin end end else begin // packet larger than max read request size - if (axi_addr_reg[12] != axi_addr_plus_max_burst[12]) begin + if (((axi_addr_reg & 12'hfff) + AXI_MAX_BURST_SIZE) >> 12 != 0) begin // crosses 4k boundary tr_count = 13'h1000 - axi_addr_reg[11:0]; last_tr = 1'b0;