Alex Forencich
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bdfeaa84ca
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Update testbenches
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2021-03-06 20:06:23 -08:00 |
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Alex Forencich
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78d755ea9a
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Minor optimization
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2021-02-28 22:31:29 -08:00 |
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Alex Forencich
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0c6bb169bc
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Rework FIFO distributed RAM init code
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2021-02-28 22:18:54 -08:00 |
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Alex Forencich
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670dfa0d11
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Fix pcie_us_axi_dma_wr testbench file list
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2021-02-28 19:50:45 -08:00 |
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Alex Forencich
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5715e12d41
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Remove tag manager module
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2021-02-28 19:37:16 -08:00 |
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Alex Forencich
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266fed8d20
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Update example design file list
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2021-02-28 19:35:35 -08:00 |
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Alex Forencich
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438a4fdcc9
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Use FIFOs for PCIe tag management in PCIe read DMA modules
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2021-02-28 19:34:24 -08:00 |
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Alex Forencich
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a3f805a0c3
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Add pipeline register
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2021-02-28 11:34:29 -08:00 |
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Alex Forencich
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92951723aa
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Offset stored address by TLP byte length to eliminate updating stored address
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2021-02-28 01:36:03 -08:00 |
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Alex Forencich
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603784b742
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Fix operation init handling
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2021-02-26 01:19:56 -08:00 |
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Alex Forencich
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912ef845a3
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Rename tag to pcie_tag
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2021-02-25 23:54:40 -08:00 |
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Alex Forencich
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062495b780
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Remove redundant parameter PCIE_EXT_TAG_ENABLE
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2021-02-25 18:20:08 -08:00 |
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Alex Forencich
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8294eecd65
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Remove redundant parameter PCIE_TAG_WIDTH
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2021-02-25 18:10:59 -08:00 |
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Alex Forencich
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8cfbe18335
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Use FIFO for op tag management in PCIe read DMA modules
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2021-02-25 16:30:23 -08:00 |
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Alex Forencich
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41d0e7cb7e
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Minor optimization
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2021-02-24 14:48:14 -08:00 |
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Alex Forencich
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63006e8092
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Add output FIFO to DMA IF mux for read response data
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2021-02-24 13:54:40 -08:00 |
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Alex Forencich
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ed29997a59
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Add write done tracking to DMA IF mux
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2021-02-24 13:51:50 -08:00 |
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Alex Forencich
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6fb2eb6b4e
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Remove unnecessary delays from testbenches
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2021-02-24 13:50:45 -08:00 |
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Alex Forencich
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40a191a06d
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Add output FIFO and write done tracking to ultrascale PCIe read DMA interface
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2021-02-24 13:50:05 -08:00 |
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Alex Forencich
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9c8417799d
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Add output FIFO and write done tracking to AXI stream sink DMA client
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2021-02-24 13:48:56 -08:00 |
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Alex Forencich
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070689692d
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Add wr_done signal to RAM model and placeholders to DMA components
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2021-02-24 13:47:53 -08:00 |
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Alex Forencich
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057a93e07a
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Sync data handling
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2021-02-16 13:56:44 -08:00 |
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Alex Forencich
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742ef1c272
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Add same-width test cases to DMA clients
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2021-02-16 01:26:05 -08:00 |
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Alex Forencich
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33bc8c21ae
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Fix bug in DMA client source when AXI stream width matches RAM interface width
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2021-02-16 01:25:07 -08:00 |
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Alex Forencich
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20b2414d7a
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Use reg instead of next for read operation generation
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2021-02-15 00:09:03 -08:00 |
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Alex Forencich
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93e2769269
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Make 64-bit-only states no-ops for other interface widths
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2021-02-14 15:17:28 -08:00 |
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Alex Forencich
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a78674c06a
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Refactor TLP header and tuser computation
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2021-02-14 11:16:25 -08:00 |
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Alex Forencich
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93496729f3
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Update testbench
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2021-02-12 16:59:13 -08:00 |
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Alex Forencich
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fb1d64e710
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Add pipeline stage to dma_if_pcie_us_wr
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2021-02-12 16:58:35 -08:00 |
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Alex Forencich
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6d98a7c0e6
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Ensure output FIFOs use distributed RAM
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2021-02-11 00:14:36 -08:00 |
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Alex Forencich
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5f7697178b
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Remove await ReadOnly
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2021-02-10 18:42:32 -08:00 |
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Alex Forencich
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ba1b0ef20b
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Add output FIFO to write DMA interface module
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2021-02-10 17:29:17 -08:00 |
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Alex Forencich
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f76ed26503
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Add output FIFO to AXI stream source DMA client
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2021-02-10 17:28:08 -08:00 |
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Alex Forencich
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c6d8983fcd
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Add wr_done output to DMA RAMs
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2021-02-07 23:47:46 -08:00 |
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Alex Forencich
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633b47ef7f
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Update XDC files
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2021-02-06 17:14:26 -08:00 |
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Alex Forencich
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5d91fde42a
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Update github actions
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2021-01-16 13:40:35 -08:00 |
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Alex Forencich
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87a6efe05c
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Rework sim_build output directory, fix default makefile target
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2020-12-29 16:26:48 -08:00 |
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Alex Forencich
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44bf507e24
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Update readme
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2020-12-19 14:59:02 -08:00 |
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Alex Forencich
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ba50df774d
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Add Github Actions regression tests
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2020-12-19 14:18:05 -08:00 |
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Alex Forencich
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8d7f4b52bf
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Add test durations
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2020-12-19 14:17:47 -08:00 |
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Alex Forencich
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0e0e9da047
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Add tox.ini
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2020-12-19 14:11:23 -08:00 |
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Alex Forencich
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a0a5ccc0a4
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Add cocotb testbenches
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2020-12-19 14:10:57 -08:00 |
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Alex Forencich
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7c19cb770d
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Properly name registers, CQ demux bug fix
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2020-12-19 14:09:56 -08:00 |
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Alex Forencich
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cabad17552
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Migrate example design testbenches to cocotb
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2020-12-18 22:10:32 -08:00 |
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Alex Forencich
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99e91c4d90
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Fix pointer handling issue in PCIe AXI DMA write module
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2020-12-18 18:37:53 -08:00 |
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Alex Forencich
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f567db764b
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Rewrite 4K address boundary crossing checks
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2020-11-11 23:54:39 -08:00 |
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Alex Forencich
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5546e40812
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Fix user_clk_frequency setting in testbenches
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2020-10-12 23:05:28 -07:00 |
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Alex Forencich
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d22d3e8bd1
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Update VCU118 XDC
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2020-10-06 00:40:16 -07:00 |
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Alex Forencich
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8f8cb39157
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Update flash programming configuration for ExaNIC X10 and X25
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2020-10-03 15:26:56 -07:00 |
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Alex Forencich
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10a6797d27
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Update VCU108 XDC
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2020-10-02 20:49:23 -07:00 |
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