FPGA/verilog-pcie
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2 Commits

Author SHA1 Message Date
Alex Forencich
c6d8983fcd Add wr_done output to DMA RAMs 2021-02-07 23:47:46 -08:00
Alex Forencich
44955d2010 Make DMA RAM module synchronous and add async variant for improved RAM inference 2020-09-25 21:49:07 -07:00