FPGA/verilog-pcie
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2 Commits

Author SHA1 Message Date
Alex Forencich
e97e4ad423 Parametrize tuser signal widths 2019-09-26 23:30:03 -07:00
Alex Forencich
c25a13041e Add Ultascale PCIe AXI lite master module and testbenches 2018-09-25 21:09:20 -07:00