273 Commits

Author SHA1 Message Date
Alex Forencich
6a02c753e9 Incrementally build tree 2018-10-14 23:43:04 -07:00
Alex Forencich
a4e2a65902 Memory writes don't get assigned tags 2018-10-14 20:30:44 -07:00
Alex Forencich
0e601554cb Set address in set_be and set_be_data 2018-10-14 20:29:34 -07:00
Alex Forencich
c047716ae8 The only locked completions are for locked memory reads 2018-10-06 17:28:21 -07:00
Alex Forencich
2059e3b16f Generate is_eof_0 2018-10-06 17:27:16 -07:00
Alex Forencich
a2a43dd11d Fix parity polarity 2018-10-06 17:00:51 -07:00
Alex Forencich
0928bf80bb Fix sign error 2018-10-02 00:26:37 -07:00
Alex Forencich
c4da967da9 Correct lower address 2018-10-01 18:08:56 -07:00
Alex Forencich
51019f0d62 Fix read TLP handling 2018-10-01 17:47:05 -07:00
Alex Forencich
00515d4342 TLP validation asserts 2018-10-01 16:16:26 -07:00
Alex Forencich
2fef5c51df Add PcieId object 2018-10-01 15:41:00 -07:00
Alex Forencich
4eb0ab240d Add fmt_type property to TLP 2018-09-30 19:14:19 -07:00
Alex Forencich
32893353d3 Improve TLP packer and unpacker error handling 2018-09-28 16:49:49 -07:00
Alex Forencich
5acd5f06fb Handle maximum length and byte count values 2018-09-28 16:48:40 -07:00
Alex Forencich
1f968f1aea Add get_id to Function, use set_completion_data 2018-09-28 16:42:17 -07:00
Alex Forencich
7c184bee59 Generate last byte enable offset correctly for single DWORD operations 2018-09-28 16:39:53 -07:00
Alex Forencich
2f279b55b3 Add has_data and status parameters to set_completion, add set_completion_data 2018-09-28 16:36:46 -07:00
Alex Forencich
16fdbba010 Fix RC packer bug 2018-09-28 01:06:36 -07:00
Alex Forencich
b5cfb9d025 Handshaking fixes 2018-09-26 20:11:25 -07:00
Alex Forencich
0bcd30501f More tests and asserts 2018-09-26 20:10:56 -07:00
Alex Forencich
c25a13041e Add Ultascale PCIe AXI lite master module and testbenches 2018-09-25 21:09:20 -07:00
Alex Forencich
f7947d883a Add AXI stream endpoint model 2018-09-25 20:55:44 -07:00
Alex Forencich
c57ef057ee Initial commit 2018-09-25 19:50:57 -07:00