Alex Forencich
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a6d64bbcbb
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Remove extraneous character
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2019-12-07 14:36:32 -08:00 |
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Alex Forencich
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7567db1818
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Add credit-based flow control to DMA cores
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2019-12-06 23:24:36 -08:00 |
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Alex Forencich
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4c8fcef230
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Add RQ sequence number inputs, TX_LIMIT parameter to ultrascale read DMA modules
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2019-11-26 16:30:30 -08:00 |
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Alex Forencich
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bbcdcc17bc
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Rename OP_TAG_WIDTH to OP_TABLE_SIZE
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2019-11-25 14:59:53 -08:00 |
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Alex Forencich
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176e1159a3
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Update python parameter computation to match verilog clog2
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2019-11-24 00:01:33 -08:00 |
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Alex Forencich
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f6f8e556ef
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Update tag parameters
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2019-11-23 21:18:46 -08:00 |
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Alex Forencich
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fdd7faef4f
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Add Xilinx Ultrascale PCIe DMA interface modules and testbenches
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2019-10-12 23:03:42 -07:00 |
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