Alex Forencich
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1b91200a4a
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Implement error code
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2019-10-01 17:17:42 -07:00 |
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Alex Forencich
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b2d9a6a77f
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Add constants
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2019-10-01 17:15:15 -07:00 |
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Alex Forencich
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4c4119d44a
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Use more correct parameters
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2019-09-30 22:36:06 -07:00 |
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Alex Forencich
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7197e17445
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Remove redundant code
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2019-09-29 12:57:48 -07:00 |
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Alex Forencich
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836246ec4d
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Add missing asserts
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2019-09-29 12:55:53 -07:00 |
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Alex Forencich
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e97e4ad423
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Parametrize tuser signal widths
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2019-09-26 23:30:03 -07:00 |
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Alex Forencich
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8678ecee65
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Fix bug in AXI operation generation
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2019-09-26 23:25:09 -07:00 |
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Alex Forencich
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e365ae44da
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Move AXI transfer size logic to improve timing
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2019-09-26 14:39:31 -07:00 |
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Alex Forencich
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cddac11486
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Bypass check when unnecessary
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2019-09-26 14:38:21 -07:00 |
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Alex Forencich
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8f73b5605f
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Fix check
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2019-09-26 14:37:41 -07:00 |
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Alex Forencich
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49f9524aeb
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Update testbenches
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2019-09-17 21:46:54 -07:00 |
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Alex Forencich
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e3ad96ef07
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Add RQ channel passthrough to pcie_us_axi_dma_wr to eliminiate external mux
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2019-09-17 16:32:47 -07:00 |
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Alex Forencich
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68974e800b
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Fix completion handling bug
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2019-08-19 14:31:08 -07:00 |
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Alex Forencich
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564178a05a
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Automatically select port upstream of device when necessary
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2019-08-04 00:38:38 -07:00 |
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Alex Forencich
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97500d10f6
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Improved link speed control script
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2019-08-03 23:32:02 -07:00 |
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Alex Forencich
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f518aec219
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Include instance names in error messages
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2019-07-25 16:38:54 -07:00 |
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Alex Forencich
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c75f29c648
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Add parameter documentation
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2019-07-24 18:01:13 -07:00 |
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Alex Forencich
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7c500e6b6e
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Update axis_arb_mux
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2019-07-24 17:52:53 -07:00 |
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Alex Forencich
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8f36c4a216
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Update priority encoder
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2019-07-24 14:23:04 -07:00 |
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Alex Forencich
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6e5a3934b2
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Add get_free_tag methods
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2019-07-15 20:38:09 -07:00 |
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Alex Forencich
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4bf1205514
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Fix completion handling in function
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2019-07-15 20:25:23 -07:00 |
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Alex Forencich
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a0bd74a198
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Add Xilinx VCU118 example design
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2019-07-15 17:24:50 -07:00 |
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Alex Forencich
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b0b51fdb34
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Add Alpha Data ADM-PCIE-9V3 example design
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2019-07-15 17:23:31 -07:00 |
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Alex Forencich
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f1348db2f7
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Add Ultrascale Plus PCIe hard IP core model and testbench
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2019-07-15 17:18:39 -07:00 |
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Alex Forencich
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1d79a4375b
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Add PCIe related scripts
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2019-07-15 12:33:35 -07:00 |
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Alex Forencich
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b5e520e9da
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Add gitignore
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2019-07-15 12:29:19 -07:00 |
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Alex Forencich
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d3b24e734f
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Don't use traceSignals
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2019-07-14 21:45:10 -07:00 |
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Alex Forencich
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ece7186671
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Fix typo
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2019-07-14 21:41:21 -07:00 |
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Alex Forencich
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d99afcb2f1
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Change tag count
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2019-07-13 11:21:19 -07:00 |
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Alex Forencich
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9c176b0916
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Add ExaNIC X10 example design
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2019-07-13 11:06:29 -07:00 |
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Alex Forencich
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8ecf4a22ef
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Add pcie_us_cfg module
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2019-07-13 10:24:25 -07:00 |
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Alex Forencich
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dcd8d7cd77
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Update readme
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2019-07-12 12:15:58 -07:00 |
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Alex Forencich
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0515d354e3
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Critical path optimization
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2019-06-28 17:28:12 -07:00 |
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Alex Forencich
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4afbd71f1f
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Fanout optimization
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2019-06-28 17:24:37 -07:00 |
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Alex Forencich
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209cb7d41d
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Fix completion handling
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2019-06-12 21:29:19 -07:00 |
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Alex Forencich
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db8a2e1e96
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Parametrize cycle count widths
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2019-05-13 22:06:41 -07:00 |
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Alex Forencich
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74a75772ec
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Pipeline tag table write
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2019-05-13 19:15:43 -07:00 |
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Alex Forencich
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6810c75723
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Fix parameter
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2019-05-09 23:20:36 -07:00 |
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Alex Forencich
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2f09c69e34
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Add wrappers for word access
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2019-04-22 16:43:21 -07:00 |
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Alex Forencich
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c1c4971d73
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Use correct variable
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2019-04-09 17:54:04 -07:00 |
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Alex Forencich
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f53b7ab75e
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Fix MSI wrapper
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2019-03-27 17:42:37 -07:00 |
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Alex Forencich
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5d42112477
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Enable PCIe extended tag based on tag count
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2019-03-21 00:01:48 -07:00 |
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Alex Forencich
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b592c7d7af
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Add missing parameter
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2019-03-03 22:32:35 -08:00 |
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Alex Forencich
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56ebc966e1
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Update parameters
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2019-03-03 13:37:34 -08:00 |
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Alex Forencich
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33dceb493b
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More asserts
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2019-03-01 01:09:27 -08:00 |
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Alex Forencich
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67d31ecef0
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Set more parameters during enumeration
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2019-03-01 01:07:57 -08:00 |
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Alex Forencich
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f92c1ea980
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Reorder capability registrations
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2019-02-28 23:46:39 -08:00 |
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Alex Forencich
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1480be2173
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Rewrite capability management
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2019-02-28 23:45:23 -08:00 |
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Alex Forencich
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6baede4717
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Broadcast message support
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2019-02-15 18:04:46 -08:00 |
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Alex Forencich
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1630200cd8
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Implement proper downstream TLP routing
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2019-02-15 17:55:24 -08:00 |
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