Alex Forencich
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1dcc091201
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Adjustments for 64 bit datapath
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2018-11-26 13:17:41 -08:00 |
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Alex Forencich
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8c7eb13c0d
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Properly handle truncated packet
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2018-11-26 13:12:50 -08:00 |
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Alex Forencich
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a6809a6b57
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Use constants instead of magic numbers
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2018-11-26 13:07:50 -08:00 |
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Alex Forencich
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c3d4aeda48
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Use logical operators
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2018-11-08 23:36:05 -08:00 |
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Alex Forencich
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038688a223
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Add priority encoder and arbiter modules
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2018-10-29 17:55:47 -07:00 |
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Alex Forencich
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6e46c8e32d
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Add PCIe tag manager
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2018-10-29 17:54:10 -07:00 |
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Alex Forencich
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ff617532e0
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Add Ultrascale PCIe RC demux
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2018-10-29 17:03:19 -07:00 |
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Alex Forencich
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31e43ff7c1
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Add enable and drop ports to CQ demux
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2018-10-29 16:28:26 -07:00 |
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Alex Forencich
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4c9c493aa4
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Add Ultrascale PCIe AXI master module and testbenches
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2018-10-23 22:28:06 -07:00 |
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Alex Forencich
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d34a3e881e
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Add Ultrascale PCIe AXI master write module and testbenches
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2018-10-23 22:26:04 -07:00 |
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Alex Forencich
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3250740f96
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Add Ultrascle PCIe MSI shim
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2018-10-23 21:12:05 -07:00 |
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Alex Forencich
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8b3c9ca794
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Add pulse merge module
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2018-10-23 21:11:31 -07:00 |
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Alex Forencich
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7d5eaae4c8
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Add Ultrascle PCIe CQ demux
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2018-10-23 21:10:01 -07:00 |
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Alex Forencich
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b3ebb04491
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Add Ultrascale PCIe AXI master read module and testbenches
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2018-10-23 20:50:48 -07:00 |
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Alex Forencich
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b5cfb9d025
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Handshaking fixes
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2018-09-26 20:11:25 -07:00 |
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Alex Forencich
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c25a13041e
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Add Ultascale PCIe AXI lite master module and testbenches
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2018-09-25 21:09:20 -07:00 |
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