109 Commits

Author SHA1 Message Date
Alex Forencich
1f523f0bb4 Remove unused reg 2020-07-26 21:39:10 -07:00
Alex Forencich
dd97d2d749 Minor refactoring 2020-07-25 22:09:30 -07:00
Alex Forencich
566dfa07e7 Read DMA timing optimizations 2020-03-26 14:34:48 -07:00
Alex Forencich
08d92fd138 Add pipeline stage for memory write generation to improve completion handling throughput 2020-03-24 21:58:48 -07:00
Alex Forencich
f8ce39c585 Timing optimization 2020-03-24 19:41:02 -07:00
Alex Forencich
37934485af Timing optimization for ram_wrap computation 2020-02-28 13:22:35 -08:00
Alex Forencich
983610d6d9 Timing optimization for mask computation 2020-02-28 13:02:26 -08:00
Alex Forencich
50124ce66d Timing optimization 2020-02-28 01:01:37 -08:00
Alex Forencich
db4d0a8f94 Timing optimizations 2020-02-27 20:00:37 -08:00
Alex Forencich
092c72ba66 Compute req_last_tlp in advance 2020-02-27 18:19:45 -08:00
Alex Forencich
18bf537f4f Fix register size 2020-02-27 15:47:18 -08:00
Alex Forencich
a00589e5a3 Timing optimizations 2020-02-27 15:24:24 -08:00
Alex Forencich
ec2ceb8e56 Timing optimizations 2020-01-24 13:51:30 -08:00
Alex Forencich
e14f6c6f0e Remove unused signals 2019-12-13 15:33:12 -08:00
Alex Forencich
dfd9744b3e PCIe DMA write bandwidth optimizations 2019-12-13 15:31:37 -08:00
Alex Forencich
7567db1818 Add credit-based flow control to DMA cores 2019-12-06 23:24:36 -08:00
Alex Forencich
60a2813fbc Fix indentation 2019-12-05 22:09:04 -08:00
Alex Forencich
f3a6cec13a Use nonblocking assign 2019-12-03 15:47:58 -08:00
Alex Forencich
8985c6dbf3 Add RQ sequence number inputs, operation table, TX_LIMIT parameter to ultrascale write DMA modules 2019-12-03 15:46:36 -08:00
Alex Forencich
a1d0fb810f Reorganize 2019-12-02 15:27:27 -08:00
Alex Forencich
2afef8c6d8 Fix use before define 2019-12-02 15:18:08 -08:00
Alex Forencich
80dafd5870 Check FIFO depth 2019-12-02 15:15:24 -08:00
Alex Forencich
2dbe6e19ab Reset mask FIFO pointers 2019-12-02 14:07:17 -08:00
Alex Forencich
546ef162dd Rewrite reset 2019-11-26 16:44:46 -08:00
Alex Forencich
4c8fcef230 Add RQ sequence number inputs, TX_LIMIT parameter to ultrascale read DMA modules 2019-11-26 16:30:30 -08:00
Alex Forencich
bbcdcc17bc Rename OP_TAG_WIDTH to OP_TABLE_SIZE 2019-11-25 14:59:53 -08:00
Alex Forencich
ee532a2472 Check tag count based on target device 2019-11-15 14:57:23 -08:00
Alex Forencich
52c502227f Remove unused client tag ports and parameters 2019-11-15 00:55:13 -08:00
Alex Forencich
c43a3eb41a Fix latch inference 2019-10-22 16:03:58 -07:00
Alex Forencich
458a7fc598 Prioritize read request passthrough 2019-10-20 23:30:16 -07:00
Alex Forencich
771c3af93f Remove debug code 2019-10-20 23:21:21 -07:00
Alex Forencich
edfb962bf5 Byte enable computation optimizations 2019-10-17 11:41:56 -07:00
Alex Forencich
19ae70dcaa Fix bad optimization 2019-10-16 00:30:10 -07:00
Alex Forencich
b0c97e8d23 Add missing parameter connection 2019-10-14 23:52:38 -07:00
Alex Forencich
3a791afd37 Update DMA interface modules to support 512 bit interface 2019-10-14 16:23:18 -07:00
Alex Forencich
553d7e05fe Update AXI DMA modules to support 512 bit interface 2019-10-14 16:22:09 -07:00
Alex Forencich
f8bc6c31e5 Update AXI master modules to support 512 bit interface 2019-10-14 16:20:46 -07:00
Alex Forencich
128c9ca015 Update demux modules to support 512 bit interface 2019-10-14 16:01:38 -07:00
Alex Forencich
af09059248 Update AXI lite master module to support 512 bit interface 2019-10-14 15:58:38 -07:00
Alex Forencich
89ff925545 Timing optimizations 2019-10-14 14:00:55 -07:00
Alex Forencich
75563c65f0 Add DMA interface mux modules 2019-10-12 23:08:21 -07:00
Alex Forencich
fdd7faef4f Add Xilinx Ultrascale PCIe DMA interface modules and testbenches 2019-10-12 23:03:42 -07:00
Alex Forencich
25de311347 Add DMA RAM module 2019-10-12 22:48:23 -07:00
Alex Forencich
e1035ed57d Add AXI stream sink DMA client module and testbench 2019-10-12 22:35:57 -07:00
Alex Forencich
baeeb8ea5c Add AXI stream source DMA client module and testbench 2019-10-12 22:34:15 -07:00
Alex Forencich
a92722173a Handle ultrascale plus interface widths 2019-10-04 16:29:11 -07:00
Alex Forencich
e7630ef350 Expose parameter in wrapper 2019-10-02 23:21:49 -07:00
Alex Forencich
1b98af9364 Fix part-select range 2019-10-01 22:00:03 -07:00
Alex Forencich
4c4119d44a Use more correct parameters 2019-09-30 22:36:06 -07:00
Alex Forencich
7197e17445 Remove redundant code 2019-09-29 12:57:48 -07:00