Alex Forencich
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209cb7d41d
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Fix completion handling
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2019-06-12 21:29:19 -07:00 |
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Alex Forencich
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db8a2e1e96
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Parametrize cycle count widths
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2019-05-13 22:06:41 -07:00 |
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Alex Forencich
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74a75772ec
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Pipeline tag table write
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2019-05-13 19:15:43 -07:00 |
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Alex Forencich
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6810c75723
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Fix parameter
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2019-05-09 23:20:36 -07:00 |
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Alex Forencich
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2f09c69e34
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Add wrappers for word access
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2019-04-22 16:43:21 -07:00 |
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Alex Forencich
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c1c4971d73
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Use correct variable
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2019-04-09 17:54:04 -07:00 |
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Alex Forencich
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f53b7ab75e
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Fix MSI wrapper
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2019-03-27 17:42:37 -07:00 |
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Alex Forencich
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5d42112477
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Enable PCIe extended tag based on tag count
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2019-03-21 00:01:48 -07:00 |
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Alex Forencich
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b592c7d7af
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Add missing parameter
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2019-03-03 22:32:35 -08:00 |
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Alex Forencich
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56ebc966e1
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Update parameters
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2019-03-03 13:37:34 -08:00 |
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Alex Forencich
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33dceb493b
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More asserts
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2019-03-01 01:09:27 -08:00 |
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Alex Forencich
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67d31ecef0
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Set more parameters during enumeration
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2019-03-01 01:07:57 -08:00 |
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Alex Forencich
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f92c1ea980
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Reorder capability registrations
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2019-02-28 23:46:39 -08:00 |
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Alex Forencich
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1480be2173
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Rewrite capability management
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2019-02-28 23:45:23 -08:00 |
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Alex Forencich
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6baede4717
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Broadcast message support
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2019-02-15 18:04:46 -08:00 |
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Alex Forencich
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1630200cd8
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Implement proper downstream TLP routing
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2019-02-15 17:55:24 -08:00 |
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Alex Forencich
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178133498b
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Fix indentation
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2019-02-15 17:23:33 -08:00 |
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Alex Forencich
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13d35569fa
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Match IO bars for routing IO operations
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2019-02-15 17:23:14 -08:00 |
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Alex Forencich
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35a4d62fb8
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Split SwitchBridge into separate upstream and downstream ports
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2019-02-15 16:56:21 -08:00 |
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Alex Forencich
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247bca01f3
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Add default_switch_port parameter
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2019-02-15 15:26:09 -08:00 |
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Alex Forencich
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8cb607be04
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Fix calls to read and write root complex regions
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2019-02-15 14:40:24 -08:00 |
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Alex Forencich
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9f36acebc2
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Print TLP payloads in hex
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2019-01-28 18:17:21 -08:00 |
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Alex Forencich
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667b5c42c5
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Add support for registering MSI callbacks
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2019-01-28 16:30:19 -08:00 |
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Alex Forencich
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201c5faa80
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Always ready on RC channel in idle for 64 bits
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2019-01-22 23:00:17 -08:00 |
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Alex Forencich
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4422b908bf
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Backpressure for awvalid
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2019-01-22 22:54:40 -08:00 |
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Alex Forencich
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fac972bfe6
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RC channel backpressure fix
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2019-01-22 22:50:15 -08:00 |
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Alex Forencich
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263bb5c670
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Index based on correct tag value
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2019-01-22 22:47:15 -08:00 |
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Alex Forencich
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d86fb594c5
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More fixes for tlp_cmd backpressure
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2019-01-12 00:37:38 -08:00 |
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Alex Forencich
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5c24dcc1df
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Ensure tlp_cmd registers are clear when generating a new request
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2019-01-11 01:27:52 -08:00 |
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Alex Forencich
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5cf9597201
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Only generate a request if a tag is available
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2019-01-10 19:00:19 -08:00 |
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Alex Forencich
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73ece8451d
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Update readme
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2019-01-07 21:40:54 -08:00 |
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Alex Forencich
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bb4fa0bfa0
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Update testbenches
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2019-01-02 02:00:46 -08:00 |
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Alex Forencich
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852d583282
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Only store value when it is transferred
|
2019-01-02 01:59:29 -08:00 |
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Alex Forencich
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9b572ad0ac
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Fix bug
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2019-01-02 01:59:05 -08:00 |
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Alex Forencich
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0a33ed17a7
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Use correct parameter
|
2018-12-27 21:53:45 -08:00 |
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Alex Forencich
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c7958e1689
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Add PCIe AXI DMA descriptor mux module
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2018-12-27 19:02:15 -08:00 |
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Alex Forencich
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fbec32e4f2
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Use whole status FIFO memory
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2018-12-06 17:36:12 -08:00 |
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Alex Forencich
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5db9cddf6e
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Reorganize and simplify burst length computation code
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2018-11-29 15:20:01 -08:00 |
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Alex Forencich
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8ab02e4220
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Remove some debug code
|
2018-11-28 11:14:26 -08:00 |
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Alex Forencich
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89c8e87f95
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Add status FIFO to manage write responses
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2018-11-28 11:13:53 -08:00 |
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Alex Forencich
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c6f342ef01
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Respect enable signal
|
2018-11-28 01:18:48 -08:00 |
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Alex Forencich
|
89c52d4eec
|
Fix bit width warning
|
2018-11-26 23:27:06 -08:00 |
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Alex Forencich
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061756f667
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Add AXI stream mux module
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2018-11-26 23:25:46 -08:00 |
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Alex Forencich
|
28fa143ae5
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Add Ultrascale PCIe DMA modules and testbenches
|
2018-11-26 23:23:54 -08:00 |
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Alex Forencich
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008a7167c7
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Add AXI_MAX_BURST_SIZE parameter to PCIe AXI master
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2018-11-26 18:03:54 -08:00 |
|
Alex Forencich
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d81ee9487a
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Add some more comments
|
2018-11-26 15:56:13 -08:00 |
|
Alex Forencich
|
24f709573c
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Only store on valid transfer in
|
2018-11-26 13:18:38 -08:00 |
|
Alex Forencich
|
1dcc091201
|
Adjustments for 64 bit datapath
|
2018-11-26 13:17:41 -08:00 |
|
Alex Forencich
|
8c7eb13c0d
|
Properly handle truncated packet
|
2018-11-26 13:12:50 -08:00 |
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Alex Forencich
|
a6809a6b57
|
Use constants instead of magic numbers
|
2018-11-26 13:07:50 -08:00 |
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