Alex Forencich
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2dbe6e19ab
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Reset mask FIFO pointers
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2019-12-02 14:07:17 -08:00 |
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Alex Forencich
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a7be8e8f87
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Clear the sequence number valid bits
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2019-11-27 16:43:15 -08:00 |
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Alex Forencich
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546ef162dd
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Rewrite reset
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2019-11-26 16:44:46 -08:00 |
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Alex Forencich
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4c8fcef230
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Add RQ sequence number inputs, TX_LIMIT parameter to ultrascale read DMA modules
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2019-11-26 16:30:30 -08:00 |
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Alex Forencich
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c5a0d05b47
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Add OP_TABLE_SIZE parameter to testbenches
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2019-11-26 00:00:49 -08:00 |
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Alex Forencich
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e7bd0a62f1
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Implement RQ sequence numbers in Ultrascale models
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2019-11-25 18:07:49 -08:00 |
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Alex Forencich
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bbcdcc17bc
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Rename OP_TAG_WIDTH to OP_TABLE_SIZE
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2019-11-25 14:59:53 -08:00 |
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Alex Forencich
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176e1159a3
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Update python parameter computation to match verilog clog2
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2019-11-24 00:01:33 -08:00 |
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Alex Forencich
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f6f8e556ef
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Update tag parameters
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2019-11-23 21:18:46 -08:00 |
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Alex Forencich
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6c6e3c8212
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Remove extraneous parameter connections
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2019-11-23 21:15:33 -08:00 |
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Alex Forencich
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b2c5004962
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Fix discontinue masks
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2019-11-23 00:20:21 -08:00 |
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Alex Forencich
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a77effe885
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Remove quotes
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2019-11-17 12:51:13 -08:00 |
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Alex Forencich
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ee532a2472
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Check tag count based on target device
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2019-11-15 14:57:23 -08:00 |
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Alex Forencich
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52c502227f
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Remove unused client tag ports and parameters
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2019-11-15 00:55:13 -08:00 |
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Alex Forencich
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34c97150e8
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Fix get_free_tag
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2019-11-04 14:11:24 -08:00 |
|
Alex Forencich
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097244162e
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Add VCU108 example design
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2019-11-01 18:19:23 -07:00 |
|
Alex Forencich
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4fcea4e875
|
Add ExaNIC X25 example design
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2019-10-30 17:13:25 -07:00 |
|
Alex Forencich
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c9193109d1
|
Rename example designs
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2019-10-30 16:48:58 -07:00 |
|
Alex Forencich
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c43a3eb41a
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Fix latch inference
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2019-10-22 16:03:58 -07:00 |
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Alex Forencich
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458a7fc598
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Prioritize read request passthrough
|
2019-10-20 23:30:16 -07:00 |
|
Alex Forencich
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771c3af93f
|
Remove debug code
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2019-10-20 23:21:21 -07:00 |
|
Alex Forencich
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f2694d8ba3
|
Update readme
|
2019-10-17 19:50:49 -07:00 |
|
Alex Forencich
|
edfb962bf5
|
Byte enable computation optimizations
|
2019-10-17 11:41:56 -07:00 |
|
Alex Forencich
|
19ae70dcaa
|
Fix bad optimization
|
2019-10-16 00:30:10 -07:00 |
|
Alex Forencich
|
b0c97e8d23
|
Add missing parameter connection
|
2019-10-14 23:52:38 -07:00 |
|
Alex Forencich
|
3a791afd37
|
Update DMA interface modules to support 512 bit interface
|
2019-10-14 16:23:18 -07:00 |
|
Alex Forencich
|
553d7e05fe
|
Update AXI DMA modules to support 512 bit interface
|
2019-10-14 16:22:09 -07:00 |
|
Alex Forencich
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f8bc6c31e5
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Update AXI master modules to support 512 bit interface
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2019-10-14 16:20:46 -07:00 |
|
Alex Forencich
|
128c9ca015
|
Update demux modules to support 512 bit interface
|
2019-10-14 16:01:38 -07:00 |
|
Alex Forencich
|
af09059248
|
Update AXI lite master module to support 512 bit interface
|
2019-10-14 15:58:38 -07:00 |
|
Alex Forencich
|
39200d84cb
|
Update simulation models to support 512 bit interface
|
2019-10-14 15:45:41 -07:00 |
|
Alex Forencich
|
89ff925545
|
Timing optimizations
|
2019-10-14 14:00:55 -07:00 |
|
Alex Forencich
|
e96ee85356
|
Update example designs
|
2019-10-13 17:16:01 -07:00 |
|
Alex Forencich
|
2c43a6e189
|
Use mmap objects instead of bytearrays
|
2019-10-13 15:41:12 -07:00 |
|
Alex Forencich
|
75563c65f0
|
Add DMA interface mux modules
|
2019-10-12 23:08:21 -07:00 |
|
Alex Forencich
|
fdd7faef4f
|
Add Xilinx Ultrascale PCIe DMA interface modules and testbenches
|
2019-10-12 23:03:42 -07:00 |
|
Alex Forencich
|
25de311347
|
Add DMA RAM module
|
2019-10-12 22:48:23 -07:00 |
|
Alex Forencich
|
e1035ed57d
|
Add AXI stream sink DMA client module and testbench
|
2019-10-12 22:35:57 -07:00 |
|
Alex Forencich
|
baeeb8ea5c
|
Add AXI stream source DMA client module and testbench
|
2019-10-12 22:34:15 -07:00 |
|
Alex Forencich
|
5e9254d519
|
Check is_eof_0 in RCSink
|
2019-10-12 18:58:27 -07:00 |
|
Alex Forencich
|
9b5a5db4d1
|
Add USPcieFrame intermediate format
|
2019-10-12 18:01:39 -07:00 |
|
Alex Forencich
|
603a6e18e2
|
Fix RC channel sideband byte enables
|
2019-10-11 14:16:44 -07:00 |
|
Alex Forencich
|
b7a505acfd
|
Add segmented DMA RAM simulation model
|
2019-10-08 15:14:32 -07:00 |
|
Alex Forencich
|
a92722173a
|
Handle ultrascale plus interface widths
|
2019-10-04 16:29:11 -07:00 |
|
Alex Forencich
|
e7630ef350
|
Expose parameter in wrapper
|
2019-10-02 23:21:49 -07:00 |
|
Alex Forencich
|
1b98af9364
|
Fix part-select range
|
2019-10-01 22:00:03 -07:00 |
|
Alex Forencich
|
295b6a507e
|
Use constants instead of magic numbers
|
2019-10-01 17:30:09 -07:00 |
|
Alex Forencich
|
3817736aa1
|
Use constants instead of magic numbers
|
2019-10-01 17:24:18 -07:00 |
|
Alex Forencich
|
1b91200a4a
|
Implement error code
|
2019-10-01 17:17:42 -07:00 |
|
Alex Forencich
|
b2d9a6a77f
|
Add constants
|
2019-10-01 17:15:15 -07:00 |
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