7 Commits

Author SHA1 Message Date
Alex Forencich
4c8fcef230 Add RQ sequence number inputs, TX_LIMIT parameter to ultrascale read DMA modules 2019-11-26 16:30:30 -08:00
Alex Forencich
c5a0d05b47 Add OP_TABLE_SIZE parameter to testbenches 2019-11-26 00:00:49 -08:00
Alex Forencich
f6f8e556ef Update tag parameters 2019-11-23 21:18:46 -08:00
Alex Forencich
6c6e3c8212 Remove extraneous parameter connections 2019-11-23 21:15:33 -08:00
Alex Forencich
52c502227f Remove unused client tag ports and parameters 2019-11-15 00:55:13 -08:00
Alex Forencich
e97e4ad423 Parametrize tuser signal widths 2019-09-26 23:30:03 -07:00
Alex Forencich
28fa143ae5 Add Ultrascale PCIe DMA modules and testbenches 2018-11-26 23:23:54 -08:00