FPGA/verilog-pcie
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3 Commits

Author SHA1 Message Date
Alex Forencich
e97e4ad423 Parametrize tuser signal widths 2019-09-26 23:30:03 -07:00
Alex Forencich
008a7167c7 Add AXI_MAX_BURST_SIZE parameter to PCIe AXI master 2018-11-26 18:03:54 -08:00
Alex Forencich
4c9c493aa4 Add Ultrascale PCIe AXI master module and testbenches 2018-10-23 22:28:06 -07:00