Alex Forencich
|
51019f0d62
|
Fix read TLP handling
|
2018-10-01 17:47:05 -07:00 |
|
Alex Forencich
|
00515d4342
|
TLP validation asserts
|
2018-10-01 16:16:26 -07:00 |
|
Alex Forencich
|
2fef5c51df
|
Add PcieId object
|
2018-10-01 15:41:00 -07:00 |
|
Alex Forencich
|
4eb0ab240d
|
Add fmt_type property to TLP
|
2018-09-30 19:14:19 -07:00 |
|
Alex Forencich
|
32893353d3
|
Improve TLP packer and unpacker error handling
|
2018-09-28 16:49:49 -07:00 |
|
Alex Forencich
|
5acd5f06fb
|
Handle maximum length and byte count values
|
2018-09-28 16:48:40 -07:00 |
|
Alex Forencich
|
1f968f1aea
|
Add get_id to Function, use set_completion_data
|
2018-09-28 16:42:17 -07:00 |
|
Alex Forencich
|
7c184bee59
|
Generate last byte enable offset correctly for single DWORD operations
|
2018-09-28 16:39:53 -07:00 |
|
Alex Forencich
|
2f279b55b3
|
Add has_data and status parameters to set_completion, add set_completion_data
|
2018-09-28 16:36:46 -07:00 |
|
Alex Forencich
|
16fdbba010
|
Fix RC packer bug
|
2018-09-28 01:06:36 -07:00 |
|
Alex Forencich
|
b5cfb9d025
|
Handshaking fixes
|
2018-09-26 20:11:25 -07:00 |
|
Alex Forencich
|
0bcd30501f
|
More tests and asserts
|
2018-09-26 20:10:56 -07:00 |
|
Alex Forencich
|
c25a13041e
|
Add Ultascale PCIe AXI lite master module and testbenches
|
2018-09-25 21:09:20 -07:00 |
|
Alex Forencich
|
f7947d883a
|
Add AXI stream endpoint model
|
2018-09-25 20:55:44 -07:00 |
|
Alex Forencich
|
c57ef057ee
|
Initial commit
|
2018-09-25 19:50:57 -07:00 |
|