FPGA/verilog-pcie
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3 Commits

Author SHA1 Message Date
Alex Forencich
564178a05a Automatically select port upstream of device when necessary 2019-08-04 00:38:38 -07:00
Alex Forencich
97500d10f6 Improved link speed control script 2019-08-03 23:32:02 -07:00
Alex Forencich
1d79a4375b Add PCIe related scripts 2019-07-15 12:33:35 -07:00