Alex Forencich
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5c24dcc1df
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Ensure tlp_cmd registers are clear when generating a new request
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2019-01-11 01:27:52 -08:00 |
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Alex Forencich
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5cf9597201
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Only generate a request if a tag is available
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2019-01-10 19:00:19 -08:00 |
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Alex Forencich
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9b572ad0ac
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Fix bug
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2019-01-02 01:59:05 -08:00 |
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Alex Forencich
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fbec32e4f2
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Use whole status FIFO memory
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2018-12-06 17:36:12 -08:00 |
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Alex Forencich
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5db9cddf6e
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Reorganize and simplify burst length computation code
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2018-11-29 15:20:01 -08:00 |
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Alex Forencich
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8ab02e4220
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Remove some debug code
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2018-11-28 11:14:26 -08:00 |
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Alex Forencich
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89c8e87f95
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Add status FIFO to manage write responses
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2018-11-28 11:13:53 -08:00 |
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Alex Forencich
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c6f342ef01
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Respect enable signal
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2018-11-28 01:18:48 -08:00 |
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Alex Forencich
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28fa143ae5
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Add Ultrascale PCIe DMA modules and testbenches
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2018-11-26 23:23:54 -08:00 |
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