Alex Forencich
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5dbb771958
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Add AU280 AXI example design
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2020-07-12 11:42:48 -07:00 |
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Alex Forencich
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ebae4e436d
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Update AXI simulation model
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2020-07-02 21:28:35 -07:00 |
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Alex Forencich
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281e1a2156
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Convert to TCL IP
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2020-07-01 23:53:58 -07:00 |
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Alex Forencich
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d6ad22d435
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Add DMA block diagram
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2020-05-07 12:36:37 -07:00 |
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Alex Forencich
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6e974aca27
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Driver update for Linux kernel API change
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2020-03-26 16:12:56 -07:00 |
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Alex Forencich
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566dfa07e7
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Read DMA timing optimizations
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2020-03-26 14:34:48 -07:00 |
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Alex Forencich
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08d92fd138
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Add pipeline stage for memory write generation to improve completion handling throughput
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2020-03-24 21:58:48 -07:00 |
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Alex Forencich
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f8ce39c585
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Timing optimization
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2020-03-24 19:41:02 -07:00 |
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Alex Forencich
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060320010d
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Don't configure MSI if already configured
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2020-03-02 21:16:09 -08:00 |
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Alex Forencich
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37934485af
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Timing optimization for ram_wrap computation
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2020-02-28 13:22:35 -08:00 |
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Alex Forencich
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983610d6d9
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Timing optimization for mask computation
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2020-02-28 13:02:26 -08:00 |
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Alex Forencich
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50124ce66d
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Timing optimization
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2020-02-28 01:01:37 -08:00 |
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Alex Forencich
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db4d0a8f94
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Timing optimizations
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2020-02-27 20:00:37 -08:00 |
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Alex Forencich
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092c72ba66
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Compute req_last_tlp in advance
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2020-02-27 18:19:45 -08:00 |
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Alex Forencich
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18bf537f4f
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Fix register size
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2020-02-27 15:47:18 -08:00 |
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Alex Forencich
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a00589e5a3
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Timing optimizations
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2020-02-27 15:24:24 -08:00 |
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Alex Forencich
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bd0482fc96
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Update script for sysfs changes
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2020-02-26 12:21:36 -08:00 |
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Alex Forencich
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8d087ecc92
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Consolidate example driver code
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2020-02-13 13:16:05 -08:00 |
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Alex Forencich
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ec2ceb8e56
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Timing optimizations
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2020-01-24 13:51:30 -08:00 |
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Alex Forencich
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3bad28d626
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Add VCU1525 AXI example design
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2020-01-15 22:43:33 -08:00 |
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Alex Forencich
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e14f6c6f0e
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Remove unused signals
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2019-12-13 15:33:12 -08:00 |
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Alex Forencich
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dfd9744b3e
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PCIe DMA write bandwidth optimizations
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2019-12-13 15:31:37 -08:00 |
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Alex Forencich
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a6d64bbcbb
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Remove extraneous character
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2019-12-07 14:36:32 -08:00 |
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Alex Forencich
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d561195dc8
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Add get_data_credits to TLP
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2019-12-07 00:54:16 -08:00 |
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Alex Forencich
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7567db1818
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Add credit-based flow control to DMA cores
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2019-12-06 23:24:36 -08:00 |
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Alex Forencich
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00858212c6
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Placeholder values for flow control credit outputs
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2019-12-06 19:16:05 -08:00 |
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Alex Forencich
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60a2813fbc
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Fix indentation
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2019-12-05 22:09:04 -08:00 |
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Alex Forencich
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f3a6cec13a
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Use nonblocking assign
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2019-12-03 15:47:58 -08:00 |
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Alex Forencich
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8985c6dbf3
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Add RQ sequence number inputs, operation table, TX_LIMIT parameter to ultrascale write DMA modules
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2019-12-03 15:46:36 -08:00 |
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Alex Forencich
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a1d0fb810f
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Reorganize
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2019-12-02 15:27:27 -08:00 |
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Alex Forencich
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2afef8c6d8
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Fix use before define
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2019-12-02 15:18:08 -08:00 |
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Alex Forencich
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80dafd5870
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Check FIFO depth
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2019-12-02 15:15:24 -08:00 |
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Alex Forencich
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2dbe6e19ab
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Reset mask FIFO pointers
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2019-12-02 14:07:17 -08:00 |
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Alex Forencich
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a7be8e8f87
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Clear the sequence number valid bits
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2019-11-27 16:43:15 -08:00 |
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Alex Forencich
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546ef162dd
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Rewrite reset
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2019-11-26 16:44:46 -08:00 |
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Alex Forencich
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4c8fcef230
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Add RQ sequence number inputs, TX_LIMIT parameter to ultrascale read DMA modules
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2019-11-26 16:30:30 -08:00 |
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Alex Forencich
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c5a0d05b47
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Add OP_TABLE_SIZE parameter to testbenches
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2019-11-26 00:00:49 -08:00 |
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Alex Forencich
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e7bd0a62f1
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Implement RQ sequence numbers in Ultrascale models
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2019-11-25 18:07:49 -08:00 |
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Alex Forencich
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bbcdcc17bc
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Rename OP_TAG_WIDTH to OP_TABLE_SIZE
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2019-11-25 14:59:53 -08:00 |
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Alex Forencich
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176e1159a3
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Update python parameter computation to match verilog clog2
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2019-11-24 00:01:33 -08:00 |
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Alex Forencich
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f6f8e556ef
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Update tag parameters
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2019-11-23 21:18:46 -08:00 |
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Alex Forencich
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6c6e3c8212
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Remove extraneous parameter connections
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2019-11-23 21:15:33 -08:00 |
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Alex Forencich
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b2c5004962
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Fix discontinue masks
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2019-11-23 00:20:21 -08:00 |
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Alex Forencich
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a77effe885
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Remove quotes
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2019-11-17 12:51:13 -08:00 |
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Alex Forencich
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ee532a2472
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Check tag count based on target device
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2019-11-15 14:57:23 -08:00 |
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Alex Forencich
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52c502227f
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Remove unused client tag ports and parameters
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2019-11-15 00:55:13 -08:00 |
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Alex Forencich
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34c97150e8
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Fix get_free_tag
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2019-11-04 14:11:24 -08:00 |
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Alex Forencich
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097244162e
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Add VCU108 example design
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2019-11-01 18:19:23 -07:00 |
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Alex Forencich
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4fcea4e875
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Add ExaNIC X25 example design
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2019-10-30 17:13:25 -07:00 |
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Alex Forencich
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c9193109d1
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Rename example designs
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2019-10-30 16:48:58 -07:00 |
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