Alex Forencich
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fbec32e4f2
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Use whole status FIFO memory
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2018-12-06 17:36:12 -08:00 |
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Alex Forencich
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5db9cddf6e
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Reorganize and simplify burst length computation code
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2018-11-29 15:20:01 -08:00 |
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Alex Forencich
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8ab02e4220
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Remove some debug code
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2018-11-28 11:14:26 -08:00 |
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Alex Forencich
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89c8e87f95
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Add status FIFO to manage write responses
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2018-11-28 11:13:53 -08:00 |
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Alex Forencich
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c6f342ef01
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Respect enable signal
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2018-11-28 01:18:48 -08:00 |
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Alex Forencich
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89c52d4eec
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Fix bit width warning
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2018-11-26 23:27:06 -08:00 |
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Alex Forencich
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061756f667
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Add AXI stream mux module
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2018-11-26 23:25:46 -08:00 |
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Alex Forencich
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28fa143ae5
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Add Ultrascale PCIe DMA modules and testbenches
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2018-11-26 23:23:54 -08:00 |
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Alex Forencich
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008a7167c7
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Add AXI_MAX_BURST_SIZE parameter to PCIe AXI master
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2018-11-26 18:03:54 -08:00 |
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Alex Forencich
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d81ee9487a
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Add some more comments
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2018-11-26 15:56:13 -08:00 |
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Alex Forencich
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24f709573c
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Only store on valid transfer in
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2018-11-26 13:18:38 -08:00 |
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Alex Forencich
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1dcc091201
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Adjustments for 64 bit datapath
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2018-11-26 13:17:41 -08:00 |
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Alex Forencich
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8c7eb13c0d
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Properly handle truncated packet
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2018-11-26 13:12:50 -08:00 |
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Alex Forencich
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a6809a6b57
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Use constants instead of magic numbers
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2018-11-26 13:07:50 -08:00 |
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Alex Forencich
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c3d4aeda48
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Use logical operators
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2018-11-08 23:36:05 -08:00 |
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Alex Forencich
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038688a223
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Add priority encoder and arbiter modules
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2018-10-29 17:55:47 -07:00 |
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Alex Forencich
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6e46c8e32d
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Add PCIe tag manager
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2018-10-29 17:54:10 -07:00 |
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Alex Forencich
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ff617532e0
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Add Ultrascale PCIe RC demux
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2018-10-29 17:03:19 -07:00 |
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Alex Forencich
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31e43ff7c1
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Add enable and drop ports to CQ demux
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2018-10-29 16:28:26 -07:00 |
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Alex Forencich
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e0b2416100
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Add AXI model
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2018-10-23 22:39:12 -07:00 |
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Alex Forencich
|
4c9c493aa4
|
Add Ultrascale PCIe AXI master module and testbenches
|
2018-10-23 22:28:06 -07:00 |
|
Alex Forencich
|
d34a3e881e
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Add Ultrascale PCIe AXI master write module and testbenches
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2018-10-23 22:26:04 -07:00 |
|
Alex Forencich
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5a02ba2cb1
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Use yield from more consistently
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2018-10-23 21:24:39 -07:00 |
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Alex Forencich
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3250740f96
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Add Ultrascle PCIe MSI shim
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2018-10-23 21:12:05 -07:00 |
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Alex Forencich
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8b3c9ca794
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Add pulse merge module
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2018-10-23 21:11:31 -07:00 |
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Alex Forencich
|
7d5eaae4c8
|
Add Ultrascle PCIe CQ demux
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2018-10-23 21:10:01 -07:00 |
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Alex Forencich
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b3ebb04491
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Add Ultrascale PCIe AXI master read module and testbenches
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2018-10-23 20:50:48 -07:00 |
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Alex Forencich
|
ab82ea5296
|
Match IP core ordering
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2018-10-16 18:02:28 -07:00 |
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Alex Forencich
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6f9c2a1ed2
|
Add MSI support to Ultrascale PCIe model
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2018-10-15 14:18:27 -07:00 |
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Alex Forencich
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35ccc2ffd5
|
Add pause signals
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2018-10-15 14:17:00 -07:00 |
|
Alex Forencich
|
4adaa480ca
|
Mask out old field value
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2018-10-15 13:52:05 -07:00 |
|
Alex Forencich
|
22850707a6
|
Address is relative to beginning of region
|
2018-10-15 13:51:43 -07:00 |
|
Alex Forencich
|
be8ef351ce
|
Fix off-by-one error
|
2018-10-15 13:51:19 -07:00 |
|
Alex Forencich
|
8ada97200f
|
Update signal widths
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2018-10-15 13:41:29 -07:00 |
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Alex Forencich
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325df5152f
|
Don't reimplement mem_write for MSI and MSI-X
|
2018-10-15 11:39:33 -07:00 |
|
Alex Forencich
|
15fdbfeba7
|
Add attr and tc parameters to mem_read and mem_write
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2018-10-15 11:35:37 -07:00 |
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Alex Forencich
|
e19c84c092
|
Add msi_register_signal
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2018-10-15 10:37:35 -07:00 |
|
Alex Forencich
|
bafae02651
|
Add MSI test
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2018-10-15 00:10:39 -07:00 |
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Alex Forencich
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997db1e141
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Implment MSI support in RootComplex
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2018-10-15 00:08:22 -07:00 |
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Alex Forencich
|
80c8e01bfd
|
Add issue_msi_interrupt and issue_msix_interrupt
|
2018-10-15 00:07:40 -07:00 |
|
Alex Forencich
|
45f3614afb
|
Add MSI_CAP_LEN and MSIX_CAP_LEN
|
2018-10-15 00:06:57 -07:00 |
|
Alex Forencich
|
76dccafe0e
|
Consolidate MSI capability objects
|
2018-10-15 00:05:37 -07:00 |
|
Alex Forencich
|
2b9e4ccb78
|
Add get_capability_offset to TreeItem
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2018-10-15 00:00:13 -07:00 |
|
Alex Forencich
|
cbd1577129
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yield config_read and config_write
|
2018-10-14 23:59:03 -07:00 |
|
Alex Forencich
|
9f4e62333a
|
Rename parameter to dev
|
2018-10-14 23:57:53 -07:00 |
|
Alex Forencich
|
6a02c753e9
|
Incrementally build tree
|
2018-10-14 23:43:04 -07:00 |
|
Alex Forencich
|
a4e2a65902
|
Memory writes don't get assigned tags
|
2018-10-14 20:30:44 -07:00 |
|
Alex Forencich
|
0e601554cb
|
Set address in set_be and set_be_data
|
2018-10-14 20:29:34 -07:00 |
|
Alex Forencich
|
c047716ae8
|
The only locked completions are for locked memory reads
|
2018-10-06 17:28:21 -07:00 |
|
Alex Forencich
|
2059e3b16f
|
Generate is_eof_0
|
2018-10-06 17:27:16 -07:00 |
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