Alex Forencich
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75563c65f0
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Add DMA interface mux modules
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2019-10-12 23:08:21 -07:00 |
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Alex Forencich
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fdd7faef4f
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Add Xilinx Ultrascale PCIe DMA interface modules and testbenches
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2019-10-12 23:03:42 -07:00 |
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Alex Forencich
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25de311347
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Add DMA RAM module
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2019-10-12 22:48:23 -07:00 |
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Alex Forencich
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e1035ed57d
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Add AXI stream sink DMA client module and testbench
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2019-10-12 22:35:57 -07:00 |
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Alex Forencich
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baeeb8ea5c
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Add AXI stream source DMA client module and testbench
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2019-10-12 22:34:15 -07:00 |
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Alex Forencich
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a92722173a
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Handle ultrascale plus interface widths
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2019-10-04 16:29:11 -07:00 |
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Alex Forencich
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e7630ef350
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Expose parameter in wrapper
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2019-10-02 23:21:49 -07:00 |
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Alex Forencich
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1b98af9364
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Fix part-select range
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2019-10-01 22:00:03 -07:00 |
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Alex Forencich
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4c4119d44a
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Use more correct parameters
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2019-09-30 22:36:06 -07:00 |
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Alex Forencich
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7197e17445
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Remove redundant code
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2019-09-29 12:57:48 -07:00 |
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Alex Forencich
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e97e4ad423
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Parametrize tuser signal widths
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2019-09-26 23:30:03 -07:00 |
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Alex Forencich
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8678ecee65
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Fix bug in AXI operation generation
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2019-09-26 23:25:09 -07:00 |
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Alex Forencich
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e365ae44da
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Move AXI transfer size logic to improve timing
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2019-09-26 14:39:31 -07:00 |
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Alex Forencich
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cddac11486
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Bypass check when unnecessary
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2019-09-26 14:38:21 -07:00 |
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Alex Forencich
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8f73b5605f
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Fix check
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2019-09-26 14:37:41 -07:00 |
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Alex Forencich
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e3ad96ef07
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Add RQ channel passthrough to pcie_us_axi_dma_wr to eliminiate external mux
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2019-09-17 16:32:47 -07:00 |
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Alex Forencich
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68974e800b
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Fix completion handling bug
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2019-08-19 14:31:08 -07:00 |
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Alex Forencich
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f518aec219
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Include instance names in error messages
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2019-07-25 16:38:54 -07:00 |
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Alex Forencich
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c75f29c648
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Add parameter documentation
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2019-07-24 18:01:13 -07:00 |
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Alex Forencich
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7c500e6b6e
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Update axis_arb_mux
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2019-07-24 17:52:53 -07:00 |
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Alex Forencich
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8f36c4a216
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Update priority encoder
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2019-07-24 14:23:04 -07:00 |
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Alex Forencich
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8ecf4a22ef
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Add pcie_us_cfg module
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2019-07-13 10:24:25 -07:00 |
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Alex Forencich
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0515d354e3
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Critical path optimization
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2019-06-28 17:28:12 -07:00 |
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Alex Forencich
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4afbd71f1f
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Fanout optimization
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2019-06-28 17:24:37 -07:00 |
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Alex Forencich
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db8a2e1e96
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Parametrize cycle count widths
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2019-05-13 22:06:41 -07:00 |
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Alex Forencich
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74a75772ec
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Pipeline tag table write
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2019-05-13 19:15:43 -07:00 |
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Alex Forencich
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c1c4971d73
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Use correct variable
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2019-04-09 17:54:04 -07:00 |
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Alex Forencich
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f53b7ab75e
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Fix MSI wrapper
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2019-03-27 17:42:37 -07:00 |
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Alex Forencich
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5d42112477
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Enable PCIe extended tag based on tag count
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2019-03-21 00:01:48 -07:00 |
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Alex Forencich
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b592c7d7af
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Add missing parameter
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2019-03-03 22:32:35 -08:00 |
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Alex Forencich
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56ebc966e1
|
Update parameters
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2019-03-03 13:37:34 -08:00 |
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Alex Forencich
|
201c5faa80
|
Always ready on RC channel in idle for 64 bits
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2019-01-22 23:00:17 -08:00 |
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Alex Forencich
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4422b908bf
|
Backpressure for awvalid
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2019-01-22 22:54:40 -08:00 |
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Alex Forencich
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fac972bfe6
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RC channel backpressure fix
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2019-01-22 22:50:15 -08:00 |
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Alex Forencich
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263bb5c670
|
Index based on correct tag value
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2019-01-22 22:47:15 -08:00 |
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Alex Forencich
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d86fb594c5
|
More fixes for tlp_cmd backpressure
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2019-01-12 00:37:38 -08:00 |
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Alex Forencich
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5c24dcc1df
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Ensure tlp_cmd registers are clear when generating a new request
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2019-01-11 01:27:52 -08:00 |
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Alex Forencich
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5cf9597201
|
Only generate a request if a tag is available
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2019-01-10 19:00:19 -08:00 |
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Alex Forencich
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852d583282
|
Only store value when it is transferred
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2019-01-02 01:59:29 -08:00 |
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Alex Forencich
|
9b572ad0ac
|
Fix bug
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2019-01-02 01:59:05 -08:00 |
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Alex Forencich
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0a33ed17a7
|
Use correct parameter
|
2018-12-27 21:53:45 -08:00 |
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Alex Forencich
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c7958e1689
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Add PCIe AXI DMA descriptor mux module
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2018-12-27 19:02:15 -08:00 |
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Alex Forencich
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fbec32e4f2
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Use whole status FIFO memory
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2018-12-06 17:36:12 -08:00 |
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Alex Forencich
|
5db9cddf6e
|
Reorganize and simplify burst length computation code
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2018-11-29 15:20:01 -08:00 |
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Alex Forencich
|
8ab02e4220
|
Remove some debug code
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2018-11-28 11:14:26 -08:00 |
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Alex Forencich
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89c8e87f95
|
Add status FIFO to manage write responses
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2018-11-28 11:13:53 -08:00 |
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Alex Forencich
|
c6f342ef01
|
Respect enable signal
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2018-11-28 01:18:48 -08:00 |
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Alex Forencich
|
89c52d4eec
|
Fix bit width warning
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2018-11-26 23:27:06 -08:00 |
|
Alex Forencich
|
061756f667
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Add AXI stream mux module
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2018-11-26 23:25:46 -08:00 |
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Alex Forencich
|
28fa143ae5
|
Add Ultrascale PCIe DMA modules and testbenches
|
2018-11-26 23:23:54 -08:00 |
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