Alex Forencich
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7c500e6b6e
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Update axis_arb_mux
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2019-07-24 17:52:53 -07:00 |
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Alex Forencich
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8f36c4a216
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Update priority encoder
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2019-07-24 14:23:04 -07:00 |
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Alex Forencich
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8ecf4a22ef
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Add pcie_us_cfg module
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2019-07-13 10:24:25 -07:00 |
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Alex Forencich
|
0515d354e3
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Critical path optimization
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2019-06-28 17:28:12 -07:00 |
|
Alex Forencich
|
4afbd71f1f
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Fanout optimization
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2019-06-28 17:24:37 -07:00 |
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Alex Forencich
|
db8a2e1e96
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Parametrize cycle count widths
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2019-05-13 22:06:41 -07:00 |
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Alex Forencich
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74a75772ec
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Pipeline tag table write
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2019-05-13 19:15:43 -07:00 |
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Alex Forencich
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c1c4971d73
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Use correct variable
|
2019-04-09 17:54:04 -07:00 |
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Alex Forencich
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f53b7ab75e
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Fix MSI wrapper
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2019-03-27 17:42:37 -07:00 |
|
Alex Forencich
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5d42112477
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Enable PCIe extended tag based on tag count
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2019-03-21 00:01:48 -07:00 |
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Alex Forencich
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b592c7d7af
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Add missing parameter
|
2019-03-03 22:32:35 -08:00 |
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Alex Forencich
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56ebc966e1
|
Update parameters
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2019-03-03 13:37:34 -08:00 |
|
Alex Forencich
|
201c5faa80
|
Always ready on RC channel in idle for 64 bits
|
2019-01-22 23:00:17 -08:00 |
|
Alex Forencich
|
4422b908bf
|
Backpressure for awvalid
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2019-01-22 22:54:40 -08:00 |
|
Alex Forencich
|
fac972bfe6
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RC channel backpressure fix
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2019-01-22 22:50:15 -08:00 |
|
Alex Forencich
|
263bb5c670
|
Index based on correct tag value
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2019-01-22 22:47:15 -08:00 |
|
Alex Forencich
|
d86fb594c5
|
More fixes for tlp_cmd backpressure
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2019-01-12 00:37:38 -08:00 |
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Alex Forencich
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5c24dcc1df
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Ensure tlp_cmd registers are clear when generating a new request
|
2019-01-11 01:27:52 -08:00 |
|
Alex Forencich
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5cf9597201
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Only generate a request if a tag is available
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2019-01-10 19:00:19 -08:00 |
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Alex Forencich
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852d583282
|
Only store value when it is transferred
|
2019-01-02 01:59:29 -08:00 |
|
Alex Forencich
|
9b572ad0ac
|
Fix bug
|
2019-01-02 01:59:05 -08:00 |
|
Alex Forencich
|
0a33ed17a7
|
Use correct parameter
|
2018-12-27 21:53:45 -08:00 |
|
Alex Forencich
|
c7958e1689
|
Add PCIe AXI DMA descriptor mux module
|
2018-12-27 19:02:15 -08:00 |
|
Alex Forencich
|
fbec32e4f2
|
Use whole status FIFO memory
|
2018-12-06 17:36:12 -08:00 |
|
Alex Forencich
|
5db9cddf6e
|
Reorganize and simplify burst length computation code
|
2018-11-29 15:20:01 -08:00 |
|
Alex Forencich
|
8ab02e4220
|
Remove some debug code
|
2018-11-28 11:14:26 -08:00 |
|
Alex Forencich
|
89c8e87f95
|
Add status FIFO to manage write responses
|
2018-11-28 11:13:53 -08:00 |
|
Alex Forencich
|
c6f342ef01
|
Respect enable signal
|
2018-11-28 01:18:48 -08:00 |
|
Alex Forencich
|
89c52d4eec
|
Fix bit width warning
|
2018-11-26 23:27:06 -08:00 |
|
Alex Forencich
|
061756f667
|
Add AXI stream mux module
|
2018-11-26 23:25:46 -08:00 |
|
Alex Forencich
|
28fa143ae5
|
Add Ultrascale PCIe DMA modules and testbenches
|
2018-11-26 23:23:54 -08:00 |
|
Alex Forencich
|
008a7167c7
|
Add AXI_MAX_BURST_SIZE parameter to PCIe AXI master
|
2018-11-26 18:03:54 -08:00 |
|
Alex Forencich
|
d81ee9487a
|
Add some more comments
|
2018-11-26 15:56:13 -08:00 |
|
Alex Forencich
|
24f709573c
|
Only store on valid transfer in
|
2018-11-26 13:18:38 -08:00 |
|
Alex Forencich
|
1dcc091201
|
Adjustments for 64 bit datapath
|
2018-11-26 13:17:41 -08:00 |
|
Alex Forencich
|
8c7eb13c0d
|
Properly handle truncated packet
|
2018-11-26 13:12:50 -08:00 |
|
Alex Forencich
|
a6809a6b57
|
Use constants instead of magic numbers
|
2018-11-26 13:07:50 -08:00 |
|
Alex Forencich
|
c3d4aeda48
|
Use logical operators
|
2018-11-08 23:36:05 -08:00 |
|
Alex Forencich
|
038688a223
|
Add priority encoder and arbiter modules
|
2018-10-29 17:55:47 -07:00 |
|
Alex Forencich
|
6e46c8e32d
|
Add PCIe tag manager
|
2018-10-29 17:54:10 -07:00 |
|
Alex Forencich
|
ff617532e0
|
Add Ultrascale PCIe RC demux
|
2018-10-29 17:03:19 -07:00 |
|
Alex Forencich
|
31e43ff7c1
|
Add enable and drop ports to CQ demux
|
2018-10-29 16:28:26 -07:00 |
|
Alex Forencich
|
4c9c493aa4
|
Add Ultrascale PCIe AXI master module and testbenches
|
2018-10-23 22:28:06 -07:00 |
|
Alex Forencich
|
d34a3e881e
|
Add Ultrascale PCIe AXI master write module and testbenches
|
2018-10-23 22:26:04 -07:00 |
|
Alex Forencich
|
3250740f96
|
Add Ultrascle PCIe MSI shim
|
2018-10-23 21:12:05 -07:00 |
|
Alex Forencich
|
8b3c9ca794
|
Add pulse merge module
|
2018-10-23 21:11:31 -07:00 |
|
Alex Forencich
|
7d5eaae4c8
|
Add Ultrascle PCIe CQ demux
|
2018-10-23 21:10:01 -07:00 |
|
Alex Forencich
|
b3ebb04491
|
Add Ultrascale PCIe AXI master read module and testbenches
|
2018-10-23 20:50:48 -07:00 |
|
Alex Forencich
|
b5cfb9d025
|
Handshaking fixes
|
2018-09-26 20:11:25 -07:00 |
|
Alex Forencich
|
c25a13041e
|
Add Ultascale PCIe AXI lite master module and testbenches
|
2018-09-25 21:09:20 -07:00 |
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