FPGA/verilog-pcie
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3 Commits

Author SHA1 Message Date
Alex Forencich
8985c6dbf3 Add RQ sequence number inputs, operation table, TX_LIMIT parameter to ultrascale write DMA modules 2019-12-03 15:46:36 -08:00
Alex Forencich
176e1159a3 Update python parameter computation to match verilog clog2 2019-11-24 00:01:33 -08:00
Alex Forencich
3a791afd37 Update DMA interface modules to support 512 bit interface 2019-10-14 16:23:18 -07:00