FPGA/verilog-pcie
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4 Commits

Author SHA1 Message Date
Alex Forencich
836246ec4d Add missing asserts 2019-09-29 12:55:53 -07:00
Alex Forencich
e97e4ad423 Parametrize tuser signal widths 2019-09-26 23:30:03 -07:00
Alex Forencich
e3ad96ef07 Add RQ channel passthrough to pcie_us_axi_dma_wr to eliminiate external mux 2019-09-17 16:32:47 -07:00
Alex Forencich
28fa143ae5 Add Ultrascale PCIe DMA modules and testbenches 2018-11-26 23:23:54 -08:00