Alex Forencich
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9c8417799d
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Add output FIFO and write done tracking to AXI stream sink DMA client
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2021-02-24 13:48:56 -08:00 |
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Alex Forencich
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070689692d
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Add wr_done signal to RAM model and placeholders to DMA components
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2021-02-24 13:47:53 -08:00 |
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Alex Forencich
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057a93e07a
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Sync data handling
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2021-02-16 13:56:44 -08:00 |
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Alex Forencich
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1e75c3cc70
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Fix AXI stream DMA client bug causing dropped writes when widths are the same
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2020-08-06 21:32:10 -07:00 |
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Alex Forencich
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0d4e9989c8
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Fix asserts
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2020-08-06 21:31:58 -07:00 |
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Alex Forencich
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e1035ed57d
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Add AXI stream sink DMA client module and testbench
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2019-10-12 22:35:57 -07:00 |
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