Alex Forencich
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7567db1818
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Add credit-based flow control to DMA cores
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2019-12-06 23:24:36 -08:00 |
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Alex Forencich
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4c8fcef230
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Add RQ sequence number inputs, TX_LIMIT parameter to ultrascale read DMA modules
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2019-11-26 16:30:30 -08:00 |
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Alex Forencich
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c5a0d05b47
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Add OP_TABLE_SIZE parameter to testbenches
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2019-11-26 00:00:49 -08:00 |
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Alex Forencich
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176e1159a3
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Update python parameter computation to match verilog clog2
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2019-11-24 00:01:33 -08:00 |
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Alex Forencich
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f6f8e556ef
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Update tag parameters
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2019-11-23 21:18:46 -08:00 |
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Alex Forencich
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52c502227f
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Remove unused client tag ports and parameters
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2019-11-15 00:55:13 -08:00 |
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Alex Forencich
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836246ec4d
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Add missing asserts
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2019-09-29 12:55:53 -07:00 |
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Alex Forencich
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e97e4ad423
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Parametrize tuser signal widths
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2019-09-26 23:30:03 -07:00 |
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Alex Forencich
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bb4fa0bfa0
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Update testbenches
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2019-01-02 02:00:46 -08:00 |
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Alex Forencich
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28fa143ae5
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Add Ultrascale PCIe DMA modules and testbenches
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2018-11-26 23:23:54 -08:00 |
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