FPGA/verilog-pcie
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2 Commits

Author SHA1 Message Date
Alex Forencich
9b5a5db4d1 Add USPcieFrame intermediate format 2019-10-12 18:01:39 -07:00
Alex Forencich
f1348db2f7 Add Ultrascale Plus PCIe hard IP core model and testbench 2019-07-15 17:18:39 -07:00