Alex Forencich
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c43a3eb41a
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Fix latch inference
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2019-10-22 16:03:58 -07:00 |
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Alex Forencich
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458a7fc598
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Prioritize read request passthrough
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2019-10-20 23:30:16 -07:00 |
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Alex Forencich
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771c3af93f
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Remove debug code
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2019-10-20 23:21:21 -07:00 |
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Alex Forencich
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f2694d8ba3
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Update readme
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2019-10-17 19:50:49 -07:00 |
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Alex Forencich
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edfb962bf5
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Byte enable computation optimizations
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2019-10-17 11:41:56 -07:00 |
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Alex Forencich
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19ae70dcaa
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Fix bad optimization
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2019-10-16 00:30:10 -07:00 |
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Alex Forencich
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b0c97e8d23
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Add missing parameter connection
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2019-10-14 23:52:38 -07:00 |
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Alex Forencich
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3a791afd37
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Update DMA interface modules to support 512 bit interface
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2019-10-14 16:23:18 -07:00 |
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Alex Forencich
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553d7e05fe
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Update AXI DMA modules to support 512 bit interface
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2019-10-14 16:22:09 -07:00 |
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Alex Forencich
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f8bc6c31e5
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Update AXI master modules to support 512 bit interface
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2019-10-14 16:20:46 -07:00 |
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Alex Forencich
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128c9ca015
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Update demux modules to support 512 bit interface
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2019-10-14 16:01:38 -07:00 |
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Alex Forencich
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af09059248
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Update AXI lite master module to support 512 bit interface
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2019-10-14 15:58:38 -07:00 |
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Alex Forencich
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39200d84cb
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Update simulation models to support 512 bit interface
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2019-10-14 15:45:41 -07:00 |
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Alex Forencich
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89ff925545
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Timing optimizations
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2019-10-14 14:00:55 -07:00 |
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Alex Forencich
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e96ee85356
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Update example designs
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2019-10-13 17:16:01 -07:00 |
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Alex Forencich
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2c43a6e189
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Use mmap objects instead of bytearrays
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2019-10-13 15:41:12 -07:00 |
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Alex Forencich
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75563c65f0
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Add DMA interface mux modules
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2019-10-12 23:08:21 -07:00 |
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Alex Forencich
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fdd7faef4f
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Add Xilinx Ultrascale PCIe DMA interface modules and testbenches
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2019-10-12 23:03:42 -07:00 |
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Alex Forencich
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25de311347
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Add DMA RAM module
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2019-10-12 22:48:23 -07:00 |
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Alex Forencich
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e1035ed57d
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Add AXI stream sink DMA client module and testbench
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2019-10-12 22:35:57 -07:00 |
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Alex Forencich
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baeeb8ea5c
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Add AXI stream source DMA client module and testbench
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2019-10-12 22:34:15 -07:00 |
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Alex Forencich
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5e9254d519
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Check is_eof_0 in RCSink
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2019-10-12 18:58:27 -07:00 |
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Alex Forencich
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9b5a5db4d1
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Add USPcieFrame intermediate format
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2019-10-12 18:01:39 -07:00 |
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Alex Forencich
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603a6e18e2
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Fix RC channel sideband byte enables
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2019-10-11 14:16:44 -07:00 |
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Alex Forencich
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b7a505acfd
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Add segmented DMA RAM simulation model
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2019-10-08 15:14:32 -07:00 |
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Alex Forencich
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a92722173a
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Handle ultrascale plus interface widths
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2019-10-04 16:29:11 -07:00 |
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Alex Forencich
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e7630ef350
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Expose parameter in wrapper
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2019-10-02 23:21:49 -07:00 |
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Alex Forencich
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1b98af9364
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Fix part-select range
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2019-10-01 22:00:03 -07:00 |
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Alex Forencich
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295b6a507e
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Use constants instead of magic numbers
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2019-10-01 17:30:09 -07:00 |
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Alex Forencich
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3817736aa1
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Use constants instead of magic numbers
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2019-10-01 17:24:18 -07:00 |
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Alex Forencich
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1b91200a4a
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Implement error code
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2019-10-01 17:17:42 -07:00 |
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Alex Forencich
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b2d9a6a77f
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Add constants
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2019-10-01 17:15:15 -07:00 |
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Alex Forencich
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4c4119d44a
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Use more correct parameters
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2019-09-30 22:36:06 -07:00 |
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Alex Forencich
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7197e17445
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Remove redundant code
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2019-09-29 12:57:48 -07:00 |
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Alex Forencich
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836246ec4d
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Add missing asserts
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2019-09-29 12:55:53 -07:00 |
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Alex Forencich
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e97e4ad423
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Parametrize tuser signal widths
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2019-09-26 23:30:03 -07:00 |
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Alex Forencich
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8678ecee65
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Fix bug in AXI operation generation
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2019-09-26 23:25:09 -07:00 |
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Alex Forencich
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e365ae44da
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Move AXI transfer size logic to improve timing
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2019-09-26 14:39:31 -07:00 |
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Alex Forencich
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cddac11486
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Bypass check when unnecessary
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2019-09-26 14:38:21 -07:00 |
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Alex Forencich
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8f73b5605f
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Fix check
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2019-09-26 14:37:41 -07:00 |
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Alex Forencich
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49f9524aeb
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Update testbenches
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2019-09-17 21:46:54 -07:00 |
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Alex Forencich
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e3ad96ef07
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Add RQ channel passthrough to pcie_us_axi_dma_wr to eliminiate external mux
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2019-09-17 16:32:47 -07:00 |
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Alex Forencich
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68974e800b
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Fix completion handling bug
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2019-08-19 14:31:08 -07:00 |
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Alex Forencich
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564178a05a
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Automatically select port upstream of device when necessary
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2019-08-04 00:38:38 -07:00 |
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Alex Forencich
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97500d10f6
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Improved link speed control script
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2019-08-03 23:32:02 -07:00 |
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Alex Forencich
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f518aec219
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Include instance names in error messages
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2019-07-25 16:38:54 -07:00 |
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Alex Forencich
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c75f29c648
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Add parameter documentation
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2019-07-24 18:01:13 -07:00 |
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Alex Forencich
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7c500e6b6e
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Update axis_arb_mux
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2019-07-24 17:52:53 -07:00 |
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Alex Forencich
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8f36c4a216
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Update priority encoder
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2019-07-24 14:23:04 -07:00 |
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Alex Forencich
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6e5a3934b2
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Add get_free_tag methods
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2019-07-15 20:38:09 -07:00 |
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