Alex Forencich
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d34a3e881e
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Add Ultrascale PCIe AXI master write module and testbenches
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2018-10-23 22:26:04 -07:00 |
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Alex Forencich
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5a02ba2cb1
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Use yield from more consistently
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2018-10-23 21:24:39 -07:00 |
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Alex Forencich
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3250740f96
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Add Ultrascle PCIe MSI shim
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2018-10-23 21:12:05 -07:00 |
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Alex Forencich
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8b3c9ca794
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Add pulse merge module
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2018-10-23 21:11:31 -07:00 |
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Alex Forencich
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7d5eaae4c8
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Add Ultrascle PCIe CQ demux
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2018-10-23 21:10:01 -07:00 |
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Alex Forencich
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b3ebb04491
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Add Ultrascale PCIe AXI master read module and testbenches
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2018-10-23 20:50:48 -07:00 |
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Alex Forencich
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ab82ea5296
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Match IP core ordering
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2018-10-16 18:02:28 -07:00 |
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Alex Forencich
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6f9c2a1ed2
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Add MSI support to Ultrascale PCIe model
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2018-10-15 14:18:27 -07:00 |
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Alex Forencich
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35ccc2ffd5
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Add pause signals
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2018-10-15 14:17:00 -07:00 |
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Alex Forencich
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4adaa480ca
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Mask out old field value
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2018-10-15 13:52:05 -07:00 |
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Alex Forencich
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22850707a6
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Address is relative to beginning of region
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2018-10-15 13:51:43 -07:00 |
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Alex Forencich
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be8ef351ce
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Fix off-by-one error
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2018-10-15 13:51:19 -07:00 |
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Alex Forencich
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8ada97200f
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Update signal widths
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2018-10-15 13:41:29 -07:00 |
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Alex Forencich
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325df5152f
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Don't reimplement mem_write for MSI and MSI-X
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2018-10-15 11:39:33 -07:00 |
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Alex Forencich
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15fdbfeba7
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Add attr and tc parameters to mem_read and mem_write
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2018-10-15 11:35:37 -07:00 |
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Alex Forencich
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e19c84c092
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Add msi_register_signal
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2018-10-15 10:37:35 -07:00 |
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Alex Forencich
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bafae02651
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Add MSI test
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2018-10-15 00:10:39 -07:00 |
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Alex Forencich
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997db1e141
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Implment MSI support in RootComplex
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2018-10-15 00:08:22 -07:00 |
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Alex Forencich
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80c8e01bfd
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Add issue_msi_interrupt and issue_msix_interrupt
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2018-10-15 00:07:40 -07:00 |
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Alex Forencich
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45f3614afb
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Add MSI_CAP_LEN and MSIX_CAP_LEN
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2018-10-15 00:06:57 -07:00 |
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Alex Forencich
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76dccafe0e
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Consolidate MSI capability objects
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2018-10-15 00:05:37 -07:00 |
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Alex Forencich
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2b9e4ccb78
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Add get_capability_offset to TreeItem
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2018-10-15 00:00:13 -07:00 |
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Alex Forencich
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cbd1577129
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yield config_read and config_write
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2018-10-14 23:59:03 -07:00 |
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Alex Forencich
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9f4e62333a
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Rename parameter to dev
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2018-10-14 23:57:53 -07:00 |
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Alex Forencich
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6a02c753e9
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Incrementally build tree
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2018-10-14 23:43:04 -07:00 |
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Alex Forencich
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a4e2a65902
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Memory writes don't get assigned tags
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2018-10-14 20:30:44 -07:00 |
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Alex Forencich
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0e601554cb
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Set address in set_be and set_be_data
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2018-10-14 20:29:34 -07:00 |
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Alex Forencich
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c047716ae8
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The only locked completions are for locked memory reads
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2018-10-06 17:28:21 -07:00 |
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Alex Forencich
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2059e3b16f
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Generate is_eof_0
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2018-10-06 17:27:16 -07:00 |
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Alex Forencich
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a2a43dd11d
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Fix parity polarity
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2018-10-06 17:00:51 -07:00 |
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Alex Forencich
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0928bf80bb
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Fix sign error
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2018-10-02 00:26:37 -07:00 |
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Alex Forencich
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c4da967da9
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Correct lower address
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2018-10-01 18:08:56 -07:00 |
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Alex Forencich
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51019f0d62
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Fix read TLP handling
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2018-10-01 17:47:05 -07:00 |
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Alex Forencich
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00515d4342
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TLP validation asserts
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2018-10-01 16:16:26 -07:00 |
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Alex Forencich
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2fef5c51df
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Add PcieId object
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2018-10-01 15:41:00 -07:00 |
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Alex Forencich
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4eb0ab240d
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Add fmt_type property to TLP
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2018-09-30 19:14:19 -07:00 |
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Alex Forencich
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32893353d3
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Improve TLP packer and unpacker error handling
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2018-09-28 16:49:49 -07:00 |
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Alex Forencich
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5acd5f06fb
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Handle maximum length and byte count values
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2018-09-28 16:48:40 -07:00 |
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Alex Forencich
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1f968f1aea
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Add get_id to Function, use set_completion_data
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2018-09-28 16:42:17 -07:00 |
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Alex Forencich
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7c184bee59
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Generate last byte enable offset correctly for single DWORD operations
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2018-09-28 16:39:53 -07:00 |
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Alex Forencich
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2f279b55b3
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Add has_data and status parameters to set_completion, add set_completion_data
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2018-09-28 16:36:46 -07:00 |
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Alex Forencich
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16fdbba010
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Fix RC packer bug
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2018-09-28 01:06:36 -07:00 |
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Alex Forencich
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b5cfb9d025
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Handshaking fixes
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2018-09-26 20:11:25 -07:00 |
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Alex Forencich
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0bcd30501f
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More tests and asserts
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2018-09-26 20:10:56 -07:00 |
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Alex Forencich
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c25a13041e
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Add Ultascale PCIe AXI lite master module and testbenches
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2018-09-25 21:09:20 -07:00 |
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Alex Forencich
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f7947d883a
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Add AXI stream endpoint model
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2018-09-25 20:55:44 -07:00 |
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Alex Forencich
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c57ef057ee
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Initial commit
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2018-09-25 19:50:57 -07:00 |
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