Alex Forencich
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f3a6cec13a
|
Use nonblocking assign
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2019-12-03 15:47:58 -08:00 |
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Alex Forencich
|
8985c6dbf3
|
Add RQ sequence number inputs, operation table, TX_LIMIT parameter to ultrascale write DMA modules
|
2019-12-03 15:46:36 -08:00 |
|
Alex Forencich
|
a1d0fb810f
|
Reorganize
|
2019-12-02 15:27:27 -08:00 |
|
Alex Forencich
|
2afef8c6d8
|
Fix use before define
|
2019-12-02 15:18:08 -08:00 |
|
Alex Forencich
|
80dafd5870
|
Check FIFO depth
|
2019-12-02 15:15:24 -08:00 |
|
Alex Forencich
|
2dbe6e19ab
|
Reset mask FIFO pointers
|
2019-12-02 14:07:17 -08:00 |
|
Alex Forencich
|
546ef162dd
|
Rewrite reset
|
2019-11-26 16:44:46 -08:00 |
|
Alex Forencich
|
4c8fcef230
|
Add RQ sequence number inputs, TX_LIMIT parameter to ultrascale read DMA modules
|
2019-11-26 16:30:30 -08:00 |
|
Alex Forencich
|
bbcdcc17bc
|
Rename OP_TAG_WIDTH to OP_TABLE_SIZE
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2019-11-25 14:59:53 -08:00 |
|
Alex Forencich
|
ee532a2472
|
Check tag count based on target device
|
2019-11-15 14:57:23 -08:00 |
|
Alex Forencich
|
52c502227f
|
Remove unused client tag ports and parameters
|
2019-11-15 00:55:13 -08:00 |
|
Alex Forencich
|
c43a3eb41a
|
Fix latch inference
|
2019-10-22 16:03:58 -07:00 |
|
Alex Forencich
|
458a7fc598
|
Prioritize read request passthrough
|
2019-10-20 23:30:16 -07:00 |
|
Alex Forencich
|
771c3af93f
|
Remove debug code
|
2019-10-20 23:21:21 -07:00 |
|
Alex Forencich
|
edfb962bf5
|
Byte enable computation optimizations
|
2019-10-17 11:41:56 -07:00 |
|
Alex Forencich
|
19ae70dcaa
|
Fix bad optimization
|
2019-10-16 00:30:10 -07:00 |
|
Alex Forencich
|
b0c97e8d23
|
Add missing parameter connection
|
2019-10-14 23:52:38 -07:00 |
|
Alex Forencich
|
3a791afd37
|
Update DMA interface modules to support 512 bit interface
|
2019-10-14 16:23:18 -07:00 |
|
Alex Forencich
|
553d7e05fe
|
Update AXI DMA modules to support 512 bit interface
|
2019-10-14 16:22:09 -07:00 |
|
Alex Forencich
|
f8bc6c31e5
|
Update AXI master modules to support 512 bit interface
|
2019-10-14 16:20:46 -07:00 |
|
Alex Forencich
|
128c9ca015
|
Update demux modules to support 512 bit interface
|
2019-10-14 16:01:38 -07:00 |
|
Alex Forencich
|
af09059248
|
Update AXI lite master module to support 512 bit interface
|
2019-10-14 15:58:38 -07:00 |
|
Alex Forencich
|
89ff925545
|
Timing optimizations
|
2019-10-14 14:00:55 -07:00 |
|
Alex Forencich
|
75563c65f0
|
Add DMA interface mux modules
|
2019-10-12 23:08:21 -07:00 |
|
Alex Forencich
|
fdd7faef4f
|
Add Xilinx Ultrascale PCIe DMA interface modules and testbenches
|
2019-10-12 23:03:42 -07:00 |
|
Alex Forencich
|
25de311347
|
Add DMA RAM module
|
2019-10-12 22:48:23 -07:00 |
|
Alex Forencich
|
e1035ed57d
|
Add AXI stream sink DMA client module and testbench
|
2019-10-12 22:35:57 -07:00 |
|
Alex Forencich
|
baeeb8ea5c
|
Add AXI stream source DMA client module and testbench
|
2019-10-12 22:34:15 -07:00 |
|
Alex Forencich
|
a92722173a
|
Handle ultrascale plus interface widths
|
2019-10-04 16:29:11 -07:00 |
|
Alex Forencich
|
e7630ef350
|
Expose parameter in wrapper
|
2019-10-02 23:21:49 -07:00 |
|
Alex Forencich
|
1b98af9364
|
Fix part-select range
|
2019-10-01 22:00:03 -07:00 |
|
Alex Forencich
|
4c4119d44a
|
Use more correct parameters
|
2019-09-30 22:36:06 -07:00 |
|
Alex Forencich
|
7197e17445
|
Remove redundant code
|
2019-09-29 12:57:48 -07:00 |
|
Alex Forencich
|
e97e4ad423
|
Parametrize tuser signal widths
|
2019-09-26 23:30:03 -07:00 |
|
Alex Forencich
|
8678ecee65
|
Fix bug in AXI operation generation
|
2019-09-26 23:25:09 -07:00 |
|
Alex Forencich
|
e365ae44da
|
Move AXI transfer size logic to improve timing
|
2019-09-26 14:39:31 -07:00 |
|
Alex Forencich
|
cddac11486
|
Bypass check when unnecessary
|
2019-09-26 14:38:21 -07:00 |
|
Alex Forencich
|
8f73b5605f
|
Fix check
|
2019-09-26 14:37:41 -07:00 |
|
Alex Forencich
|
e3ad96ef07
|
Add RQ channel passthrough to pcie_us_axi_dma_wr to eliminiate external mux
|
2019-09-17 16:32:47 -07:00 |
|
Alex Forencich
|
68974e800b
|
Fix completion handling bug
|
2019-08-19 14:31:08 -07:00 |
|
Alex Forencich
|
f518aec219
|
Include instance names in error messages
|
2019-07-25 16:38:54 -07:00 |
|
Alex Forencich
|
c75f29c648
|
Add parameter documentation
|
2019-07-24 18:01:13 -07:00 |
|
Alex Forencich
|
7c500e6b6e
|
Update axis_arb_mux
|
2019-07-24 17:52:53 -07:00 |
|
Alex Forencich
|
8f36c4a216
|
Update priority encoder
|
2019-07-24 14:23:04 -07:00 |
|
Alex Forencich
|
8ecf4a22ef
|
Add pcie_us_cfg module
|
2019-07-13 10:24:25 -07:00 |
|
Alex Forencich
|
0515d354e3
|
Critical path optimization
|
2019-06-28 17:28:12 -07:00 |
|
Alex Forencich
|
4afbd71f1f
|
Fanout optimization
|
2019-06-28 17:24:37 -07:00 |
|
Alex Forencich
|
db8a2e1e96
|
Parametrize cycle count widths
|
2019-05-13 22:06:41 -07:00 |
|
Alex Forencich
|
74a75772ec
|
Pipeline tag table write
|
2019-05-13 19:15:43 -07:00 |
|
Alex Forencich
|
c1c4971d73
|
Use correct variable
|
2019-04-09 17:54:04 -07:00 |
|