Alex Forencich
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f8bc6c31e5
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Update AXI master modules to support 512 bit interface
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2019-10-14 16:20:46 -07:00 |
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Alex Forencich
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e97e4ad423
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Parametrize tuser signal widths
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2019-09-26 23:30:03 -07:00 |
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Alex Forencich
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c75f29c648
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Add parameter documentation
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2019-07-24 18:01:13 -07:00 |
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Alex Forencich
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89c52d4eec
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Fix bit width warning
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2018-11-26 23:27:06 -08:00 |
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Alex Forencich
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008a7167c7
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Add AXI_MAX_BURST_SIZE parameter to PCIe AXI master
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2018-11-26 18:03:54 -08:00 |
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Alex Forencich
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31e43ff7c1
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Add enable and drop ports to CQ demux
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2018-10-29 16:28:26 -07:00 |
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Alex Forencich
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4c9c493aa4
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Add Ultrascale PCIe AXI master module and testbenches
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2018-10-23 22:28:06 -07:00 |
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